1a47a12beSStefan Roese/* 2acf3f8daSKumar Gala * Copyright 2008-2011 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * Kumar Gala <kumar.gala@freescale.com> 4a47a12beSStefan Roese * 5a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6a47a12beSStefan Roese * project. 7a47a12beSStefan Roese * 8a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11a47a12beSStefan Roese * the License, or (at your option) any later version. 12a47a12beSStefan Roese * 13a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16a47a12beSStefan Roese * GNU General Public License for more details. 17a47a12beSStefan Roese * 18a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21a47a12beSStefan Roese * MA 02111-1307 USA 22a47a12beSStefan Roese */ 23a47a12beSStefan Roese 2425ddd1fbSWolfgang Denk#include <asm-offsets.h> 25a47a12beSStefan Roese#include <config.h> 26a47a12beSStefan Roese#include <mpc85xx.h> 27a47a12beSStefan Roese#include <version.h> 28a47a12beSStefan Roese 29a47a12beSStefan Roese#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 30a47a12beSStefan Roese 31a47a12beSStefan Roese#include <ppc_asm.tmpl> 32a47a12beSStefan Roese#include <ppc_defs.h> 33a47a12beSStefan Roese 34a47a12beSStefan Roese#include <asm/cache.h> 35a47a12beSStefan Roese#include <asm/mmu.h> 36a47a12beSStefan Roese 37a47a12beSStefan Roese/* To boot secondary cpus, we need a place for them to start up. 38a47a12beSStefan Roese * Normally, they start at 0xfffffffc, but that's usually the 39a47a12beSStefan Roese * firmware, and we don't want to have to run the firmware again. 40a47a12beSStefan Roese * Instead, the primary cpu will set the BPTR to point here to 41a47a12beSStefan Roese * this page. We then set up the core, and head to 42a47a12beSStefan Roese * start_secondary. Note that this means that the code below 43a47a12beSStefan Roese * must never exceed 1023 instructions (the branch at the end 44a47a12beSStefan Roese * would then be the 1024th). 45a47a12beSStefan Roese */ 46a47a12beSStefan Roese .globl __secondary_start_page 47a47a12beSStefan Roese .align 12 48a47a12beSStefan Roese__secondary_start_page: 49a47a12beSStefan Roese/* First do some preliminary setup */ 50a47a12beSStefan Roese lis r3, HID0_EMCP@h /* enable machine check */ 51a47a12beSStefan Roese#ifndef CONFIG_E500MC 52a47a12beSStefan Roese ori r3,r3,HID0_TBEN@l /* enable Timebase */ 53a47a12beSStefan Roese#endif 54a47a12beSStefan Roese#ifdef CONFIG_PHYS_64BIT 55a47a12beSStefan Roese ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ 56a47a12beSStefan Roese#endif 57a47a12beSStefan Roese mtspr SPRN_HID0,r3 58a47a12beSStefan Roese 59a47a12beSStefan Roese#ifndef CONFIG_E500MC 60a47a12beSStefan Roese li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 61a47a12beSStefan Roese mfspr r0,PVR 62a47a12beSStefan Roese andi. r0,r0,0xff 63a47a12beSStefan Roese cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ 64a47a12beSStefan Roese blt 1f 65a47a12beSStefan Roese /* Set MBDD bit also */ 66a47a12beSStefan Roese ori r3, r3, HID1_MBDD@l 67a47a12beSStefan Roese1: 68a47a12beSStefan Roese mtspr SPRN_HID1,r3 69a47a12beSStefan Roese#endif 70a47a12beSStefan Roese 7143f082bbSKumar Gala#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 7243f082bbSKumar Gala mfspr r3,977 7343f082bbSKumar Gala oris r3,r3,0x0100 7443f082bbSKumar Gala mtspr 977,r3 7543f082bbSKumar Gala#endif 7643f082bbSKumar Gala 77a47a12beSStefan Roese /* Enable branch prediction */ 78a47a12beSStefan Roese lis r3,BUCSR_ENABLE@h 79a47a12beSStefan Roese ori r3,r3,BUCSR_ENABLE@l 80a47a12beSStefan Roese mtspr SPRN_BUCSR,r3 81a47a12beSStefan Roese 82a47a12beSStefan Roese /* Ensure TB is 0 */ 83a47a12beSStefan Roese li r3,0 84a47a12beSStefan Roese mttbl r3 85a47a12beSStefan Roese mttbu r3 86a47a12beSStefan Roese 87a47a12beSStefan Roese /* Enable/invalidate the I-Cache */ 88a47a12beSStefan Roese lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 89a47a12beSStefan Roese ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 90a47a12beSStefan Roese mtspr SPRN_L1CSR1,r2 91a47a12beSStefan Roese1: 92a47a12beSStefan Roese mfspr r3,SPRN_L1CSR1 93a47a12beSStefan Roese and. r1,r3,r2 94a47a12beSStefan Roese bne 1b 95a47a12beSStefan Roese 96a47a12beSStefan Roese lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 97a47a12beSStefan Roese ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 98a47a12beSStefan Roese mtspr SPRN_L1CSR1,r3 99a47a12beSStefan Roese isync 100a47a12beSStefan Roese2: 101a47a12beSStefan Roese mfspr r3,SPRN_L1CSR1 102a47a12beSStefan Roese andi. r1,r3,L1CSR1_ICE@l 103a47a12beSStefan Roese beq 2b 104a47a12beSStefan Roese 105a47a12beSStefan Roese /* Enable/invalidate the D-Cache */ 106a47a12beSStefan Roese lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 107a47a12beSStefan Roese ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 108a47a12beSStefan Roese mtspr SPRN_L1CSR0,r2 109a47a12beSStefan Roese1: 110a47a12beSStefan Roese mfspr r3,SPRN_L1CSR0 111a47a12beSStefan Roese and. r1,r3,r2 112a47a12beSStefan Roese bne 1b 113a47a12beSStefan Roese 114a47a12beSStefan Roese lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 115a47a12beSStefan Roese ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 116a47a12beSStefan Roese mtspr SPRN_L1CSR0,r3 117a47a12beSStefan Roese isync 118a47a12beSStefan Roese2: 119a47a12beSStefan Roese mfspr r3,SPRN_L1CSR0 120a47a12beSStefan Roese andi. r1,r3,L1CSR0_DCE@l 121a47a12beSStefan Roese beq 2b 122a47a12beSStefan Roese 123a47a12beSStefan Roese#define toreset(x) (x - __secondary_start_page + 0xfffff000) 124a47a12beSStefan Roese 125a47a12beSStefan Roese /* get our PIR to figure out our table entry */ 126a47a12beSStefan Roese lis r3,toreset(__spin_table)@h 127a47a12beSStefan Roese ori r3,r3,toreset(__spin_table)@l 128a47a12beSStefan Roese 129a47a12beSStefan Roese /* r10 has the base address for the entry */ 130a47a12beSStefan Roese mfspr r0,SPRN_PIR 131a47a12beSStefan Roese#ifdef CONFIG_E500MC 132a47a12beSStefan Roese rlwinm r4,r0,27,27,31 133a47a12beSStefan Roese#else 134a47a12beSStefan Roese mr r4,r0 135a47a12beSStefan Roese#endif 136a47a12beSStefan Roese slwi r8,r4,5 137a47a12beSStefan Roese add r10,r3,r8 138a47a12beSStefan Roese 139a47a12beSStefan Roese#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) 140a47a12beSStefan Roese /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 141a47a12beSStefan Roese slwi r8,r4,1 142a47a12beSStefan Roese addi r8,r8,32 143a47a12beSStefan Roese mtspr L1CSR2,r8 144a47a12beSStefan Roese#endif 145a47a12beSStefan Roese 146fd3c9befSKumar Gala#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) 147*1e9ea85fSYork Sun /* apply to P4080 rev 1 and rev 2 */ 148*1e9ea85fSYork Sun mfspr r3,SPRN_SVR 149*1e9ea85fSYork Sun rlwinm r3,r3,0,0xf0 150*1e9ea85fSYork Sun li r4,0x30 151*1e9ea85fSYork Sun cmpw r3,r4 152*1e9ea85fSYork Sun bge 2f 153*1e9ea85fSYork Sun 154fd3c9befSKumar Gala mfspr r8,L1CSR2 155fd3c9befSKumar Gala oris r8,r8,(L1CSR2_DCWS)@h 156fd3c9befSKumar Gala mtspr L1CSR2,r8 157*1e9ea85fSYork Sun2: 158fd3c9befSKumar Gala#endif 159fd3c9befSKumar Gala 160a47a12beSStefan Roese#ifdef CONFIG_BACKSIDE_L2_CACHE 161acf3f8daSKumar Gala /* skip L2 setup on P2040/P2040E as they have no L2 */ 162acf3f8daSKumar Gala mfspr r2,SPRN_SVR 163acf3f8daSKumar Gala lis r3,SVR_P2040@h 164acf3f8daSKumar Gala ori r3,r3,SVR_P2040@l 165acf3f8daSKumar Gala cmpw r2,r3 166acf3f8daSKumar Gala beq 3f 167acf3f8daSKumar Gala 168acf3f8daSKumar Gala lis r3,SVR_P2040_E@h 169acf3f8daSKumar Gala ori r3,r3,SVR_P2040_E@l 170acf3f8daSKumar Gala cmpw r2,r3 171acf3f8daSKumar Gala beq 3f 172acf3f8daSKumar Gala 173a47a12beSStefan Roese /* Enable/invalidate the L2 cache */ 174a47a12beSStefan Roese msync 175a47a12beSStefan Roese lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h 176a47a12beSStefan Roese ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l 177a47a12beSStefan Roese mtspr SPRN_L2CSR0,r2 178a47a12beSStefan Roese1: 179a47a12beSStefan Roese mfspr r3,SPRN_L2CSR0 180a47a12beSStefan Roese and. r1,r3,r2 181a47a12beSStefan Roese bne 1b 182a47a12beSStefan Roese 183a47a12beSStefan Roese#ifdef CONFIG_SYS_CACHE_STASHING 184a47a12beSStefan Roese /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 185a47a12beSStefan Roese addi r3,r8,1 186a47a12beSStefan Roese mtspr SPRN_L2CSR1,r3 187a47a12beSStefan Roese#endif 188a47a12beSStefan Roese 189a47a12beSStefan Roese lis r3,CONFIG_SYS_INIT_L2CSR0@h 190a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l 191a47a12beSStefan Roese mtspr SPRN_L2CSR0,r3 192a47a12beSStefan Roese isync 193a47a12beSStefan Roese2: 194a47a12beSStefan Roese mfspr r3,SPRN_L2CSR0 195a47a12beSStefan Roese andis. r1,r3,L2CSR0_L2E@h 196a47a12beSStefan Roese beq 2b 197a47a12beSStefan Roese#endif 198acf3f8daSKumar Gala3: 199a47a12beSStefan Roese 200a47a12beSStefan Roese#define EPAPR_MAGIC (0x45504150) 201a47a12beSStefan Roese#define ENTRY_ADDR_UPPER 0 202a47a12beSStefan Roese#define ENTRY_ADDR_LOWER 4 203a47a12beSStefan Roese#define ENTRY_R3_UPPER 8 204a47a12beSStefan Roese#define ENTRY_R3_LOWER 12 205a47a12beSStefan Roese#define ENTRY_RESV 16 206a47a12beSStefan Roese#define ENTRY_PIR 20 207a47a12beSStefan Roese#define ENTRY_R6_UPPER 24 208a47a12beSStefan Roese#define ENTRY_R6_LOWER 28 209a47a12beSStefan Roese#define ENTRY_SIZE 32 210a47a12beSStefan Roese 211a47a12beSStefan Roese /* setup the entry */ 212a47a12beSStefan Roese li r3,0 213a47a12beSStefan Roese li r8,1 214a47a12beSStefan Roese stw r0,ENTRY_PIR(r10) 215a47a12beSStefan Roese stw r3,ENTRY_ADDR_UPPER(r10) 216a47a12beSStefan Roese stw r8,ENTRY_ADDR_LOWER(r10) 217a47a12beSStefan Roese stw r3,ENTRY_R3_UPPER(r10) 218a47a12beSStefan Roese stw r4,ENTRY_R3_LOWER(r10) 219a47a12beSStefan Roese stw r3,ENTRY_R6_UPPER(r10) 220a47a12beSStefan Roese stw r3,ENTRY_R6_LOWER(r10) 221a47a12beSStefan Roese 222a47a12beSStefan Roese /* load r13 with the address of the 'bootpg' in SDRAM */ 223a47a12beSStefan Roese lis r13,toreset(__bootpg_addr)@h 224a47a12beSStefan Roese ori r13,r13,toreset(__bootpg_addr)@l 225a47a12beSStefan Roese lwz r13,0(r13) 226a47a12beSStefan Roese 227a47a12beSStefan Roese /* setup mapping for AS = 1, and jump there */ 228a47a12beSStefan Roese lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h 229a47a12beSStefan Roese mtspr SPRN_MAS0,r11 230a47a12beSStefan Roese lis r11,(MAS1_VALID|MAS1_IPROT)@h 231a47a12beSStefan Roese ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l 232a47a12beSStefan Roese mtspr SPRN_MAS1,r11 233a47a12beSStefan Roese oris r11,r13,(MAS2_I|MAS2_G)@h 234a47a12beSStefan Roese ori r11,r13,(MAS2_I|MAS2_G)@l 235a47a12beSStefan Roese mtspr SPRN_MAS2,r11 236a47a12beSStefan Roese oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h 237a47a12beSStefan Roese ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l 238a47a12beSStefan Roese mtspr SPRN_MAS3,r11 239a47a12beSStefan Roese tlbwe 240a47a12beSStefan Roese 241a47a12beSStefan Roese bl 1f 242a47a12beSStefan Roese1: mflr r11 243a47a12beSStefan Roese /* 244a47a12beSStefan Roese * OR in 0xfff to create a mask of the bootpg SDRAM address. We use 245a47a12beSStefan Roese * this mask to fixup the cpu spin table and the address that we want 246a47a12beSStefan Roese * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the 247a47a12beSStefan Roese * bootpg is at 0x7ffff000 in SDRAM. 248a47a12beSStefan Roese */ 249a47a12beSStefan Roese ori r13,r13,0xfff 250a47a12beSStefan Roese and r11, r11, r13 251a47a12beSStefan Roese and r10, r10, r13 252a47a12beSStefan Roese 253a47a12beSStefan Roese addi r11,r11,(2f-1b) 254a47a12beSStefan Roese mfmsr r13 255a47a12beSStefan Roese ori r12,r13,MSR_IS|MSR_DS@l 256a47a12beSStefan Roese 257a47a12beSStefan Roese mtspr SPRN_SRR0,r11 258a47a12beSStefan Roese mtspr SPRN_SRR1,r12 259a47a12beSStefan Roese rfi 260a47a12beSStefan Roese 261a47a12beSStefan Roese /* spin waiting for addr */ 262a47a12beSStefan Roese2: 263a47a12beSStefan Roese lwz r4,ENTRY_ADDR_LOWER(r10) 264a47a12beSStefan Roese andi. r11,r4,1 265a47a12beSStefan Roese bne 2b 266a47a12beSStefan Roese isync 267a47a12beSStefan Roese 268a47a12beSStefan Roese /* setup IVORs to match fixed offsets */ 269a47a12beSStefan Roese#include "fixed_ivor.S" 270a47a12beSStefan Roese 271a47a12beSStefan Roese /* get the upper bits of the addr */ 272a47a12beSStefan Roese lwz r11,ENTRY_ADDR_UPPER(r10) 273a47a12beSStefan Roese 274a47a12beSStefan Roese /* setup branch addr */ 275a47a12beSStefan Roese mtspr SPRN_SRR0,r4 276a47a12beSStefan Roese 277a47a12beSStefan Roese /* mark the entry as released */ 278a47a12beSStefan Roese li r8,3 279a47a12beSStefan Roese stw r8,ENTRY_ADDR_LOWER(r10) 280a47a12beSStefan Roese 281a47a12beSStefan Roese /* mask by ~64M to setup our tlb we will jump to */ 282a47a12beSStefan Roese rlwinm r12,r4,0,0,5 283a47a12beSStefan Roese 284a47a12beSStefan Roese /* setup r3, r4, r5, r6, r7, r8, r9 */ 285a47a12beSStefan Roese lwz r3,ENTRY_R3_LOWER(r10) 286a47a12beSStefan Roese li r4,0 287a47a12beSStefan Roese li r5,0 288a47a12beSStefan Roese lwz r6,ENTRY_R6_LOWER(r10) 289a47a12beSStefan Roese lis r7,(64*1024*1024)@h 290a47a12beSStefan Roese li r8,0 291a47a12beSStefan Roese li r9,0 292a47a12beSStefan Roese 293a47a12beSStefan Roese /* load up the pir */ 294a47a12beSStefan Roese lwz r0,ENTRY_PIR(r10) 295a47a12beSStefan Roese mtspr SPRN_PIR,r0 296a47a12beSStefan Roese mfspr r0,SPRN_PIR 297a47a12beSStefan Roese stw r0,ENTRY_PIR(r10) 298a47a12beSStefan Roese 299a47a12beSStefan Roese mtspr IVPR,r12 300a47a12beSStefan Roese/* 301a47a12beSStefan Roese * Coming here, we know the cpu has one TLB mapping in TLB1[0] 302a47a12beSStefan Roese * which maps 0xfffff000-0xffffffff one-to-one. We set up a 303a47a12beSStefan Roese * second mapping that maps addr 1:1 for 64M, and then we jump to 304a47a12beSStefan Roese * addr 305a47a12beSStefan Roese */ 306a47a12beSStefan Roese lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h 307a47a12beSStefan Roese mtspr SPRN_MAS0,r10 308a47a12beSStefan Roese lis r10,(MAS1_VALID|MAS1_IPROT)@h 309a47a12beSStefan Roese ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l 310a47a12beSStefan Roese mtspr SPRN_MAS1,r10 311a47a12beSStefan Roese /* WIMGE = 0b00000 for now */ 312a47a12beSStefan Roese mtspr SPRN_MAS2,r12 313a47a12beSStefan Roese ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR) 314a47a12beSStefan Roese mtspr SPRN_MAS3,r12 315a47a12beSStefan Roese#ifdef CONFIG_ENABLE_36BIT_PHYS 316a47a12beSStefan Roese mtspr SPRN_MAS7,r11 317a47a12beSStefan Roese#endif 318a47a12beSStefan Roese tlbwe 319a47a12beSStefan Roese 320a47a12beSStefan Roese/* Now we have another mapping for this page, so we jump to that 321a47a12beSStefan Roese * mapping 322a47a12beSStefan Roese */ 323a47a12beSStefan Roese mtspr SPRN_SRR1,r13 324a47a12beSStefan Roese rfi 325a47a12beSStefan Roese 326a47a12beSStefan Roese /* 327a47a12beSStefan Roese * Allocate some space for the SDRAM address of the bootpg. 328a47a12beSStefan Roese * This variable has to be in the boot page so that it can 329a47a12beSStefan Roese * be accessed by secondary cores when they come out of reset. 330a47a12beSStefan Roese */ 331a47a12beSStefan Roese .globl __bootpg_addr 332a47a12beSStefan Roese__bootpg_addr: 333a47a12beSStefan Roese .long 0 334a47a12beSStefan Roese 335a47a12beSStefan Roese .align L1_CACHE_SHIFT 336a47a12beSStefan Roese .globl __spin_table 337a47a12beSStefan Roese__spin_table: 338a47a12beSStefan Roese .space CONFIG_MAX_CPUS*ENTRY_SIZE 339a47a12beSStefan Roese 340a47a12beSStefan Roese /* Fill in the empty space. The actual reset vector is 341a47a12beSStefan Roese * the last word of the page */ 342a47a12beSStefan Roese__secondary_start_code_end: 343a47a12beSStefan Roese .space 4092 - (__secondary_start_code_end - __secondary_start_page) 344a47a12beSStefan Roese__secondary_reset_vector: 345a47a12beSStefan Roese b __secondary_start_page 346