xref: /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/p2041_ids.c (revision 1a0c64219df1fe4f8c40ed2ecaa0da1b4e0e26f7)
188b91f2dSKumar Gala /*
288b91f2dSKumar Gala  * Copyright 2011 Freescale Semiconductor, Inc.
388b91f2dSKumar Gala  *
488b91f2dSKumar Gala  * See file CREDITS for list of people who contributed to this
588b91f2dSKumar Gala  * project.
688b91f2dSKumar Gala  *
788b91f2dSKumar Gala  * This program is free software; you can redistribute it and/or
888b91f2dSKumar Gala  * modify it under the terms of the GNU General Public License as
988b91f2dSKumar Gala  * published by the Free Software Foundation; either version 2 of
1088b91f2dSKumar Gala  * the License, or (at your option) any later version.
1188b91f2dSKumar Gala  *
1288b91f2dSKumar Gala  * This program is distributed in the hope that it will be useful,
1388b91f2dSKumar Gala  * but WITHOUT ANY WARRANTY; without even the implied warranty of
1488b91f2dSKumar Gala  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1588b91f2dSKumar Gala  * GNU General Public License for more details.
1688b91f2dSKumar Gala  *
1788b91f2dSKumar Gala  * You should have received a copy of the GNU General Public License
1888b91f2dSKumar Gala  * along with this program; if not, write to the Free Software
1988b91f2dSKumar Gala  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2088b91f2dSKumar Gala  * MA 02111-1307 USA
2188b91f2dSKumar Gala  */
2288b91f2dSKumar Gala 
2388b91f2dSKumar Gala #include <common.h>
2488b91f2dSKumar Gala #include <asm/fsl_portals.h>
2588b91f2dSKumar Gala #include <asm/fsl_liodn.h>
2688b91f2dSKumar Gala 
2788b91f2dSKumar Gala #ifdef CONFIG_SYS_DPAA_QBMAN
2888b91f2dSKumar Gala struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
2988b91f2dSKumar Gala 	/* dqrr liodn, frame data liodn, liodn off, sdest */
3088b91f2dSKumar Gala 	SET_QP_INFO(1, 2, 1, 0),
3188b91f2dSKumar Gala 	SET_QP_INFO(3, 4, 2, 1),
3288b91f2dSKumar Gala 	SET_QP_INFO(5, 6, 3, 2),
3388b91f2dSKumar Gala 	SET_QP_INFO(7, 8, 4, 3),
34510f28cfSHaiying Wang 	SET_QP_INFO(9, 10, 5, 0),
35510f28cfSHaiying Wang 	SET_QP_INFO(11, 12, 1, 1),
36510f28cfSHaiying Wang 	SET_QP_INFO(13, 14, 2, 2),
37510f28cfSHaiying Wang 	SET_QP_INFO(15, 16, 3, 3),
38510f28cfSHaiying Wang 	SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */
39510f28cfSHaiying Wang 	SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */
4088b91f2dSKumar Gala };
4188b91f2dSKumar Gala #endif
4288b91f2dSKumar Gala 
43*1a0c6421SKumar Gala struct srio_liodn_id_table srio_liodn_tbl[] = {
44*1a0c6421SKumar Gala 	SET_SRIO_LIODN_2(1, 199, 200),
45*1a0c6421SKumar Gala 	SET_SRIO_LIODN_2(2, 201, 202),
46*1a0c6421SKumar Gala };
47*1a0c6421SKumar Gala int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
48*1a0c6421SKumar Gala 
4988b91f2dSKumar Gala struct liodn_id_table liodn_tbl[] = {
5088b91f2dSKumar Gala #ifdef CONFIG_SYS_DPAA_QBMAN
5188b91f2dSKumar Gala 	SET_QMAN_LIODN(31),
5288b91f2dSKumar Gala 	SET_BMAN_LIODN(32),
5388b91f2dSKumar Gala #endif
5488b91f2dSKumar Gala 
5588b91f2dSKumar Gala 	SET_SDHC_LIODN(1, 64),
5688b91f2dSKumar Gala 
5788b91f2dSKumar Gala 	SET_PME_LIODN(117),
5888b91f2dSKumar Gala 
5988b91f2dSKumar Gala 	SET_USB_LIODN(1, "fsl-usb2-mph", 125),
6088b91f2dSKumar Gala 	SET_USB_LIODN(2, "fsl-usb2-dr", 126),
6188b91f2dSKumar Gala 
6288b91f2dSKumar Gala 	SET_SATA_LIODN(1, 127),
6388b91f2dSKumar Gala 	SET_SATA_LIODN(2, 128),
6488b91f2dSKumar Gala 
6588b91f2dSKumar Gala 	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
6688b91f2dSKumar Gala 	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
6788b91f2dSKumar Gala 	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
6888b91f2dSKumar Gala 
6988b91f2dSKumar Gala 	SET_DMA_LIODN(1, 197),
7088b91f2dSKumar Gala 	SET_DMA_LIODN(2, 198),
7188b91f2dSKumar Gala 
7288b91f2dSKumar Gala 	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
7388b91f2dSKumar Gala 	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
7488b91f2dSKumar Gala 	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
7588b91f2dSKumar Gala 	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
7688b91f2dSKumar Gala };
7788b91f2dSKumar Gala int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
7888b91f2dSKumar Gala 
7988b91f2dSKumar Gala #ifdef CONFIG_SYS_DPAA_FMAN
8088b91f2dSKumar Gala struct liodn_id_table fman1_liodn_tbl[] = {
8188b91f2dSKumar Gala 	SET_FMAN_RX_1G_LIODN(1, 0, 10),
8288b91f2dSKumar Gala 	SET_FMAN_RX_1G_LIODN(1, 1, 11),
8388b91f2dSKumar Gala 	SET_FMAN_RX_1G_LIODN(1, 2, 12),
8488b91f2dSKumar Gala 	SET_FMAN_RX_1G_LIODN(1, 3, 13),
8588b91f2dSKumar Gala 	SET_FMAN_RX_1G_LIODN(1, 4, 14),
8688b91f2dSKumar Gala #if (CONFIG_SYS_NUM_FM1_10GEC == 1)
8788b91f2dSKumar Gala 	SET_FMAN_RX_10G_LIODN(1, 0, 15),
8888b91f2dSKumar Gala #endif
8988b91f2dSKumar Gala };
9088b91f2dSKumar Gala int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
9188b91f2dSKumar Gala #endif
9288b91f2dSKumar Gala 
9388b91f2dSKumar Gala struct liodn_id_table sec_liodn_tbl[] = {
9488b91f2dSKumar Gala 	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
9588b91f2dSKumar Gala 	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
9688b91f2dSKumar Gala 	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
9788b91f2dSKumar Gala 	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
9888b91f2dSKumar Gala 	SET_SEC_RTIC_LIODN_ENTRY(a, 154),
9988b91f2dSKumar Gala 	SET_SEC_RTIC_LIODN_ENTRY(b, 155),
10088b91f2dSKumar Gala 	SET_SEC_RTIC_LIODN_ENTRY(c, 156),
10188b91f2dSKumar Gala 	SET_SEC_RTIC_LIODN_ENTRY(d, 157),
10288b91f2dSKumar Gala 	SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
10388b91f2dSKumar Gala 	SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
10488b91f2dSKumar Gala };
10588b91f2dSKumar Gala int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
10688b91f2dSKumar Gala 
10788b91f2dSKumar Gala struct liodn_id_table liodn_bases[] = {
10888b91f2dSKumar Gala 	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 100),
10988b91f2dSKumar Gala #ifdef CONFIG_SYS_DPAA_FMAN
11088b91f2dSKumar Gala 	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
11188b91f2dSKumar Gala #endif
11288b91f2dSKumar Gala #ifdef CONFIG_SYS_DPAA_PME
11388b91f2dSKumar Gala 	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(136, 172),
11488b91f2dSKumar Gala #endif
11588b91f2dSKumar Gala };
116