1 /* 2 * Copyright 2010 Freescale Semiconductor, Inc. 3 * Author: Timur Tabi <timur@freescale.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the Free 7 * Software Foundation; either version 2 of the License, or (at your option) 8 * any later version. 9 */ 10 11 #include <config.h> 12 #include <common.h> 13 #include <asm/io.h> 14 #include <asm/immap_85xx.h> 15 #include <asm/fsl_serdes.h> 16 17 #define SRDS1_MAX_LANES 4 18 #define SRDS2_MAX_LANES 2 19 20 static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { 21 [0x00] = {NONE, NONE, NONE, NONE}, 22 [0x01] = {NONE, NONE, NONE, NONE}, 23 [0x02] = {NONE, NONE, NONE, NONE}, 24 [0x03] = {NONE, NONE, NONE, NONE}, 25 [0x04] = {NONE, NONE, NONE, NONE}, 26 [0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, 27 [0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, 28 [0x09] = {PCIE1, NONE, NONE, NONE}, 29 [0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, 30 [0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, 31 [0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, 32 [0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, 33 [0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, 34 [0x15] = {PCIE1, PCIE3, PCIE2, PCIE2}, 35 [0x16] = {PCIE1, PCIE3, PCIE2, PCIE2}, 36 [0x17] = {PCIE1, PCIE3, PCIE2, PCIE2}, 37 [0x18] = {PCIE1, PCIE1, PCIE2, PCIE2}, 38 [0x19] = {PCIE1, PCIE1, PCIE2, PCIE2}, 39 [0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2}, 40 [0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2}, 41 [0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1}, 42 [0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2}, 43 [0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2}, 44 [0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2}, 45 }; 46 47 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { 48 [0x00] = {PCIE3, PCIE3}, 49 [0x01] = {PCIE2, PCIE3}, 50 [0x02] = {SATA1, SATA2}, 51 [0x03] = {SGMII_TSEC1, SGMII_TSEC2}, 52 [0x04] = {NONE, NONE}, 53 [0x06] = {SATA1, SATA2}, 54 [0x07] = {NONE, NONE}, 55 [0x09] = {PCIE3, PCIE2}, 56 [0x0a] = {SATA1, SATA2}, 57 [0x0b] = {NONE, NONE}, 58 [0x0d] = {PCIE3, PCIE2}, 59 [0x0e] = {SATA1, SATA2}, 60 [0x0f] = {NONE, NONE}, 61 [0x15] = {SGMII_TSEC1, SGMII_TSEC2}, 62 [0x16] = {SATA1, SATA2}, 63 [0x17] = {NONE, NONE}, 64 [0x18] = {PCIE3, PCIE3}, 65 [0x19] = {SGMII_TSEC1, SGMII_TSEC2}, 66 [0x1a] = {SATA1, SATA2}, 67 [0x1b] = {NONE, NONE}, 68 [0x1c] = {PCIE3, PCIE3}, 69 [0x1d] = {SGMII_TSEC1, SGMII_TSEC2}, 70 [0x1e] = {SATA1, SATA2}, 71 [0x1f] = {NONE, NONE}, 72 }; 73 74 /* 75 * A list of PCI and SATA slots 76 */ 77 enum slot_id { 78 SLOT_PCIE1 = 1, 79 SLOT_PCIE2, 80 SLOT_PCIE3, 81 SLOT_PCIE4, 82 SLOT_PCIE5, 83 SLOT_SATA1, 84 SLOT_SATA2 85 }; 86 87 /* 88 * This array maps the slot identifiers to their names on the P1022DS board. 89 */ 90 static const char *slot_names[] = { 91 [SLOT_PCIE1] = "Slot 1", 92 [SLOT_PCIE2] = "Slot 2", 93 [SLOT_PCIE3] = "Slot 3", 94 [SLOT_PCIE4] = "Slot 4", 95 [SLOT_PCIE5] = "Mini-PCIe", 96 [SLOT_SATA1] = "SATA 1", 97 [SLOT_SATA2] = "SATA 2", 98 }; 99 100 /* 101 * This array maps a given SERDES configuration and SERDES device to the PCI or 102 * SATA slot that it connects to. This mapping is hard-coded in the FPGA. 103 */ 104 static u8 serdes_dev_slot[][SATA2 + 1] = { 105 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, 106 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 107 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, 108 [PCIE2] = SLOT_PCIE5 }, 109 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 110 [PCIE2] = SLOT_PCIE3, 111 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 112 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 113 [PCIE2] = SLOT_PCIE3 }, 114 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, 115 [PCIE2] = SLOT_PCIE3, 116 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 117 [0x1c] = { [PCIE1] = SLOT_PCIE1, 118 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 119 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, 120 [0x1f] = { [PCIE1] = SLOT_PCIE1 }, 121 }; 122 123 int is_serdes_configured(enum srds_prtcl device) 124 { 125 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 126 u32 pordevsr = in_be32(&gur->pordevsr); 127 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 128 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 129 unsigned int i; 130 131 debug("%s: dev = %d\n", __FUNCTION__, device); 132 debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg); 133 134 if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { 135 printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg); 136 return 0; 137 } 138 139 for (i = 0; i < SRDS1_MAX_LANES; i++) { 140 if (serdes1_cfg_tbl[srds_cfg][i] == device) 141 return 1; 142 if (serdes2_cfg_tbl[srds_cfg][i] == device) 143 return 1; 144 } 145 146 return 0; 147 } 148 149 /* 150 * Returns the name of the slot to which the PCIe or SATA controller is 151 * connected 152 */ 153 const char *serdes_slot_name(enum srds_prtcl device) 154 { 155 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 156 u32 pordevsr = in_be32(&gur->pordevsr); 157 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 158 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 159 enum slot_id slot = serdes_dev_slot[srds_cfg][device]; 160 const char *name = slot_names[slot]; 161 162 if (name) 163 return name; 164 else 165 return "Nothing"; 166 } 167