xref: /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c (revision cbe7706ab8aab06c18edaa9b120371f9c8012728)
1af87cab6SKumar Gala /*
2af87cab6SKumar Gala  * Copyright 2010 Freescale Semiconductor, Inc.
3af87cab6SKumar Gala  *
41a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
5af87cab6SKumar Gala  */
6af87cab6SKumar Gala 
7af87cab6SKumar Gala #include <config.h>
8af87cab6SKumar Gala #include <common.h>
9af87cab6SKumar Gala #include <asm/io.h>
10af87cab6SKumar Gala #include <asm/immap_85xx.h>
11af87cab6SKumar Gala #include <asm/fsl_serdes.h>
12af87cab6SKumar Gala 
13af87cab6SKumar Gala #define SRDS1_MAX_LANES		8
14af87cab6SKumar Gala 
15af87cab6SKumar Gala static u32 serdes1_prtcl_map;
16af87cab6SKumar Gala 
17af87cab6SKumar Gala static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
18af87cab6SKumar Gala 	[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
19af87cab6SKumar Gala 	[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
20af87cab6SKumar Gala 	[0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
21af87cab6SKumar Gala 	[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
22af87cab6SKumar Gala 	[0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
23af87cab6SKumar Gala 	[0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
24af87cab6SKumar Gala 	[0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
25af87cab6SKumar Gala 	[0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
26af87cab6SKumar Gala 	[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
27af87cab6SKumar Gala };
28af87cab6SKumar Gala 
is_serdes_configured(enum srds_prtcl prtcl)29af87cab6SKumar Gala int is_serdes_configured(enum srds_prtcl prtcl)
30af87cab6SKumar Gala {
31*71fe2225SHou Zhiqiang 	if (!(serdes1_prtcl_map & (1 << NONE)))
32*71fe2225SHou Zhiqiang 		fsl_serdes_init();
33*71fe2225SHou Zhiqiang 
34af87cab6SKumar Gala 	return (1 << prtcl) & serdes1_prtcl_map;
35af87cab6SKumar Gala }
36af87cab6SKumar Gala 
fsl_serdes_init(void)37af87cab6SKumar Gala void fsl_serdes_init(void)
38af87cab6SKumar Gala {
39af87cab6SKumar Gala 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
40af87cab6SKumar Gala 	u32 pordevsr = in_be32(&gur->pordevsr);
41af87cab6SKumar Gala 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
42af87cab6SKumar Gala 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
43af87cab6SKumar Gala 	int lane;
44af87cab6SKumar Gala 
45*71fe2225SHou Zhiqiang 	if (serdes1_prtcl_map & (1 << NONE))
46*71fe2225SHou Zhiqiang 		return;
47*71fe2225SHou Zhiqiang 
48af87cab6SKumar Gala 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
49af87cab6SKumar Gala 
50e51e47d3SAxel Lin 	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
51af87cab6SKumar Gala 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
52af87cab6SKumar Gala 		return;
53af87cab6SKumar Gala 	}
54af87cab6SKumar Gala 
55af87cab6SKumar Gala 	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
56af87cab6SKumar Gala 		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
57af87cab6SKumar Gala 		serdes1_prtcl_map |= (1 << lane_prtcl);
58af87cab6SKumar Gala 	}
59af87cab6SKumar Gala 
60af87cab6SKumar Gala 	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
61af87cab6SKumar Gala 		serdes1_prtcl_map |= (1 << SGMII_TSEC1);
62af87cab6SKumar Gala 
63af87cab6SKumar Gala 	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
64af87cab6SKumar Gala 		serdes1_prtcl_map |= (1 << SGMII_TSEC2);
65af87cab6SKumar Gala 
66af87cab6SKumar Gala 	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
67af87cab6SKumar Gala 		serdes1_prtcl_map |= (1 << SGMII_TSEC3);
68af87cab6SKumar Gala 
69af87cab6SKumar Gala 	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
70af87cab6SKumar Gala 		serdes1_prtcl_map |= (1 << SGMII_TSEC4);
71*71fe2225SHou Zhiqiang 
72*71fe2225SHou Zhiqiang 	/* Set the first bit to indicate serdes has been initialized */
73*71fe2225SHou Zhiqiang 	serdes1_prtcl_map |= (1 << NONE);
74af87cab6SKumar Gala }
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