1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/processor.h> 25 #include <ioports.h> 26 #include <lmb.h> 27 #include <asm/io.h> 28 #include <asm/mmu.h> 29 #include <asm/fsl_law.h> 30 #include <asm/fsl_ddr_sdram.h> 31 #include "mp.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 u32 fsl_ddr_get_intl3r(void); 35 36 u32 get_my_id() 37 { 38 return mfspr(SPRN_PIR); 39 } 40 41 /* 42 * Determine if U-Boot should keep secondary cores in reset, or let them out 43 * of reset and hold them in a spinloop 44 */ 45 int hold_cores_in_reset(int verbose) 46 { 47 const char *s = getenv("mp_holdoff"); 48 49 /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */ 50 if (s && (*s == 'y' || *s == 'Y' || *s == '1')) { 51 if (verbose) { 52 puts("Secondary cores are being held in reset.\n"); 53 puts("See 'mp_holdoff' environment variable\n"); 54 } 55 56 return 1; 57 } 58 59 return 0; 60 } 61 62 int cpu_reset(int nr) 63 { 64 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 65 out_be32(&pic->pir, 1 << nr); 66 /* the dummy read works around an errata on early 85xx MP PICs */ 67 (void)in_be32(&pic->pir); 68 out_be32(&pic->pir, 0x0); 69 70 return 0; 71 } 72 73 int cpu_status(int nr) 74 { 75 u32 *table, id = get_my_id(); 76 77 if (hold_cores_in_reset(1)) 78 return 0; 79 80 if (nr == id) { 81 table = (u32 *)get_spin_virt_addr(); 82 printf("table base @ 0x%p\n", table); 83 } else { 84 table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; 85 printf("Running on cpu %d\n", id); 86 printf("\n"); 87 printf("table @ 0x%p\n", table); 88 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); 89 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); 90 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); 91 printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]); 92 } 93 94 return 0; 95 } 96 97 #ifdef CONFIG_FSL_CORENET 98 int cpu_disable(int nr) 99 { 100 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 101 102 setbits_be32(&gur->coredisrl, 1 << nr); 103 104 return 0; 105 } 106 107 int is_core_disabled(int nr) { 108 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 109 u32 coredisrl = in_be32(&gur->coredisrl); 110 111 return (coredisrl & (1 << nr)); 112 } 113 #else 114 int cpu_disable(int nr) 115 { 116 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 117 118 switch (nr) { 119 case 0: 120 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0); 121 break; 122 case 1: 123 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1); 124 break; 125 default: 126 printf("Invalid cpu number for disable %d\n", nr); 127 return 1; 128 } 129 130 return 0; 131 } 132 133 int is_core_disabled(int nr) { 134 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 135 u32 devdisr = in_be32(&gur->devdisr); 136 137 switch (nr) { 138 case 0: 139 return (devdisr & MPC85xx_DEVDISR_CPU0); 140 case 1: 141 return (devdisr & MPC85xx_DEVDISR_CPU1); 142 default: 143 printf("Invalid cpu number for disable %d\n", nr); 144 } 145 146 return 0; 147 } 148 #endif 149 150 static u8 boot_entry_map[4] = { 151 0, 152 BOOT_ENTRY_PIR, 153 BOOT_ENTRY_R3_LOWER, 154 BOOT_ENTRY_R6_LOWER, 155 }; 156 157 int cpu_release(int nr, int argc, char * const argv[]) 158 { 159 u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; 160 u64 boot_addr; 161 162 if (hold_cores_in_reset(1)) 163 return 0; 164 165 if (nr == get_my_id()) { 166 printf("Invalid to release the boot core.\n\n"); 167 return 1; 168 } 169 170 if (argc != 4) { 171 printf("Invalid number of arguments to release.\n\n"); 172 return 1; 173 } 174 175 boot_addr = simple_strtoull(argv[0], NULL, 16); 176 177 /* handle pir, r3, r6 */ 178 for (i = 1; i < 4; i++) { 179 if (argv[i][0] != '-') { 180 u8 entry = boot_entry_map[i]; 181 val = simple_strtoul(argv[i], NULL, 16); 182 table[entry] = val; 183 } 184 } 185 186 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); 187 188 /* ensure all table updates complete before final address write */ 189 eieio(); 190 191 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff); 192 193 return 0; 194 } 195 196 u32 determine_mp_bootpg(unsigned int *pagesize) 197 { 198 u32 bootpg; 199 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468 200 u32 svr = get_svr(); 201 u32 granule_size, check; 202 struct law_entry e; 203 #endif 204 205 /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ 206 if ((u64)gd->ram_size > 0xfffff000) 207 bootpg = 0xfffff000; 208 else 209 bootpg = gd->ram_size - 4096; 210 if (pagesize) 211 *pagesize = 4096; 212 213 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468 214 /* 215 * Erratum A004468 has two parts. The 3-way interleaving applies to T4240, 216 * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But 217 * the way boot page chosen in u-boot avoids hitting this erratum. So only 218 * thw workaround for 3-way interleaving is needed. 219 * 220 * To make sure boot page translation works with 3-Way DDR interleaving 221 * enforce a check for the following constrains 222 * 8K granule size requires BRSIZE=8K and 223 * bootpg >> log2(BRSIZE) %3 == 1 224 * 4K and 1K granule size requires BRSIZE=4K and 225 * bootpg >> log2(BRSIZE) %3 == 0 226 */ 227 if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) { 228 e = find_law(bootpg); 229 switch (e.trgt_id) { 230 case LAW_TRGT_IF_DDR_INTLV_123: 231 granule_size = fsl_ddr_get_intl3r() & 0x1f; 232 if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) { 233 if (pagesize) 234 *pagesize = 8192; 235 bootpg &= 0xffffe000; /* align to 8KB */ 236 check = bootpg >> 13; 237 while ((check % 3) != 1) 238 check--; 239 bootpg = check << 13; 240 debug("Boot page (8K) at 0x%08x\n", bootpg); 241 break; 242 } else { 243 bootpg &= 0xfffff000; /* align to 4KB */ 244 check = bootpg >> 12; 245 while ((check % 3) != 0) 246 check--; 247 bootpg = check << 12; 248 debug("Boot page (4K) at 0x%08x\n", bootpg); 249 } 250 break; 251 default: 252 break; 253 } 254 } 255 #endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */ 256 257 return bootpg; 258 } 259 260 ulong get_spin_phys_addr(void) 261 { 262 extern ulong __secondary_start_page; 263 extern ulong __spin_table; 264 265 return (determine_mp_bootpg() + 266 (ulong)&__spin_table - (ulong)&__secondary_start_page); 267 } 268 269 ulong get_spin_virt_addr(void) 270 { 271 extern ulong __secondary_start_page; 272 extern ulong __spin_table; 273 274 return (CONFIG_BPTR_VIRT_ADDR + 275 (ulong)&__spin_table - (ulong)&__secondary_start_page); 276 } 277 278 #ifdef CONFIG_FSL_CORENET 279 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) 280 { 281 u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K; 282 u32 *table = (u32 *)get_spin_virt_addr(); 283 volatile ccsr_gur_t *gur; 284 volatile ccsr_local_t *ccm; 285 volatile ccsr_rcpm_t *rcpm; 286 volatile ccsr_pic_t *pic; 287 int timeout = 10; 288 u32 mask = cpu_mask(); 289 struct law_entry e; 290 291 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 292 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); 293 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 294 pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 295 296 whoami = in_be32(&pic->whoami); 297 cpu_up_mask = 1 << whoami; 298 out_be32(&ccm->bstrl, bootpg); 299 300 e = find_law(bootpg); 301 /* pagesize is only 4K or 8K */ 302 if (pagesize == 8192) 303 brsize = LAW_SIZE_8K; 304 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize); 305 debug("BRSIZE is 0x%x\n", brsize); 306 307 /* readback to sync write */ 308 in_be32(&ccm->bstrar); 309 310 /* disable time base at the platform */ 311 out_be32(&rcpm->ctbenrl, cpu_up_mask); 312 313 out_be32(&gur->brrl, mask); 314 315 /* wait for everyone */ 316 while (timeout) { 317 unsigned int i, cpu, nr_cpus = cpu_numcores(); 318 319 for_each_cpu(i, cpu, nr_cpus, mask) { 320 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) 321 cpu_up_mask |= (1 << cpu); 322 } 323 324 if ((cpu_up_mask & mask) == mask) 325 break; 326 327 udelay(100); 328 timeout--; 329 } 330 331 if (timeout == 0) 332 printf("CPU up timeout. CPU up mask is %x should be %x\n", 333 cpu_up_mask, mask); 334 335 /* enable time base at the platform */ 336 out_be32(&rcpm->ctbenrl, 0); 337 338 /* readback to sync write */ 339 in_be32(&rcpm->ctbenrl); 340 341 mtspr(SPRN_TBWU, 0); 342 mtspr(SPRN_TBWL, 0); 343 344 out_be32(&rcpm->ctbenrl, mask); 345 346 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR 347 /* 348 * Disabling Boot Page Translation allows the memory region 0xfffff000 349 * to 0xffffffff to be used normally. Leaving Boot Page Translation 350 * enabled remaps 0xfffff000 to SDRAM which makes that memory region 351 * unusable for normal operation but it does allow OSes to easily 352 * reset a processor core to put it back into U-Boot's spinloop. 353 */ 354 clrbits_be32(&ccm->bstrar, LAW_EN); 355 #endif 356 } 357 #else 358 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) 359 { 360 u32 up, cpu_up_mask, whoami; 361 u32 *table = (u32 *)get_spin_virt_addr(); 362 volatile u32 bpcr; 363 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 364 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 365 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 366 u32 devdisr; 367 int timeout = 10; 368 369 whoami = in_be32(&pic->whoami); 370 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); 371 372 /* disable time base at the platform */ 373 devdisr = in_be32(&gur->devdisr); 374 if (whoami) 375 devdisr |= MPC85xx_DEVDISR_TB0; 376 else 377 devdisr |= MPC85xx_DEVDISR_TB1; 378 out_be32(&gur->devdisr, devdisr); 379 380 /* release the hounds */ 381 up = ((1 << cpu_numcores()) - 1); 382 bpcr = in_be32(&ecm->eebpcr); 383 bpcr |= (up << 24); 384 out_be32(&ecm->eebpcr, bpcr); 385 asm("sync; isync; msync"); 386 387 cpu_up_mask = 1 << whoami; 388 /* wait for everyone */ 389 while (timeout) { 390 int i; 391 for (i = 0; i < cpu_numcores(); i++) { 392 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) 393 cpu_up_mask |= (1 << i); 394 }; 395 396 if ((cpu_up_mask & up) == up) 397 break; 398 399 udelay(100); 400 timeout--; 401 } 402 403 if (timeout == 0) 404 printf("CPU up timeout. CPU up mask is %x should be %x\n", 405 cpu_up_mask, up); 406 407 /* enable time base at the platform */ 408 if (whoami) 409 devdisr |= MPC85xx_DEVDISR_TB1; 410 else 411 devdisr |= MPC85xx_DEVDISR_TB0; 412 out_be32(&gur->devdisr, devdisr); 413 414 /* readback to sync write */ 415 in_be32(&gur->devdisr); 416 417 mtspr(SPRN_TBWU, 0); 418 mtspr(SPRN_TBWL, 0); 419 420 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); 421 out_be32(&gur->devdisr, devdisr); 422 423 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR 424 /* 425 * Disabling Boot Page Translation allows the memory region 0xfffff000 426 * to 0xffffffff to be used normally. Leaving Boot Page Translation 427 * enabled remaps 0xfffff000 to SDRAM which makes that memory region 428 * unusable for normal operation but it does allow OSes to easily 429 * reset a processor core to put it back into U-Boot's spinloop. 430 */ 431 clrbits_be32(&ecm->bptr, 0x80000000); 432 #endif 433 } 434 #endif 435 436 void cpu_mp_lmb_reserve(struct lmb *lmb) 437 { 438 u32 bootpg = determine_mp_bootpg(NULL); 439 440 lmb_reserve(lmb, bootpg, 4096); 441 } 442 443 void setup_mp(void) 444 { 445 extern ulong __secondary_start_page; 446 extern ulong __bootpg_addr; 447 448 ulong fixup = (ulong)&__secondary_start_page; 449 u32 bootpg, bootpg_map, pagesize; 450 451 bootpg = determine_mp_bootpg(&pagesize); 452 453 /* 454 * pagesize is only 4K or 8K 455 * we only use the last 4K of boot page 456 * bootpg_map saves the address for the boot page 457 * 8K is used for the workaround of 3-way DDR interleaving 458 */ 459 460 bootpg_map = bootpg; 461 462 if (pagesize == 8192) 463 bootpg += 4096; /* use 2nd half */ 464 465 /* Some OSes expect secondary cores to be held in reset */ 466 if (hold_cores_in_reset(0)) 467 return; 468 469 /* Store the bootpg's SDRAM address for use by secondary CPU cores */ 470 __bootpg_addr = bootpg; 471 472 /* look for the tlb covering the reset page, there better be one */ 473 int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); 474 475 /* we found a match */ 476 if (i != -1) { 477 /* map reset page to bootpg so we can copy code there */ 478 disable_tlb(i); 479 480 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ 481 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 482 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ 483 484 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); 485 486 plat_mp_up(bootpg_map, pagesize); 487 } else { 488 puts("WARNING: No reset page TLB. " 489 "Skipping secondary core setup\n"); 490 } 491 } 492