1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2000-2002 3*a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * (C) Copyright 2002 (440 port) 6*a47a12beSStefan Roese * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * (C) Copyright 2003 Motorola Inc. (MPC85xx port) 9*a47a12beSStefan Roese * Xianghua Xiao (X.Xiao@motorola.com) 10*a47a12beSStefan Roese * 11*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 12*a47a12beSStefan Roese * project. 13*a47a12beSStefan Roese * 14*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 15*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 16*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 17*a47a12beSStefan Roese * the License, or (at your option) any later version. 18*a47a12beSStefan Roese * 19*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 20*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 21*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22*a47a12beSStefan Roese * GNU General Public License for more details. 23*a47a12beSStefan Roese * 24*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 25*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 26*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27*a47a12beSStefan Roese * MA 02111-1307 USA 28*a47a12beSStefan Roese */ 29*a47a12beSStefan Roese 30*a47a12beSStefan Roese #include <common.h> 31*a47a12beSStefan Roese #include <watchdog.h> 32*a47a12beSStefan Roese #include <command.h> 33*a47a12beSStefan Roese #include <asm/processor.h> 34*a47a12beSStefan Roese #include <asm/io.h> 35*a47a12beSStefan Roese 36*a47a12beSStefan Roese int interrupt_init_cpu(unsigned int *decrementer_count) 37*a47a12beSStefan Roese { 38*a47a12beSStefan Roese ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR; 39*a47a12beSStefan Roese 40*a47a12beSStefan Roese out_be32(&pic->gcr, MPC85xx_PICGCR_RST); 41*a47a12beSStefan Roese while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) 42*a47a12beSStefan Roese ; 43*a47a12beSStefan Roese out_be32(&pic->gcr, MPC85xx_PICGCR_M); 44*a47a12beSStefan Roese in_be32(&pic->gcr); 45*a47a12beSStefan Roese 46*a47a12beSStefan Roese *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; 47*a47a12beSStefan Roese 48*a47a12beSStefan Roese /* PIE is same as DIE, dec interrupt enable */ 49*a47a12beSStefan Roese mtspr(SPRN_TCR, TCR_PIE); 50*a47a12beSStefan Roese 51*a47a12beSStefan Roese #ifdef CONFIG_INTERRUPTS 52*a47a12beSStefan Roese pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ 53*a47a12beSStefan Roese debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1); 54*a47a12beSStefan Roese 55*a47a12beSStefan Roese pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ 56*a47a12beSStefan Roese debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2); 57*a47a12beSStefan Roese 58*a47a12beSStefan Roese pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ 59*a47a12beSStefan Roese debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3); 60*a47a12beSStefan Roese 61*a47a12beSStefan Roese #ifdef CONFIG_PCI1 62*a47a12beSStefan Roese pic->iivpr8 = 0x810008; /* enable pci1 interrupts */ 63*a47a12beSStefan Roese debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8); 64*a47a12beSStefan Roese #endif 65*a47a12beSStefan Roese #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) 66*a47a12beSStefan Roese pic->iivpr9 = 0x810009; /* enable pci1 interrupts */ 67*a47a12beSStefan Roese debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9); 68*a47a12beSStefan Roese #endif 69*a47a12beSStefan Roese #ifdef CONFIG_PCIE1 70*a47a12beSStefan Roese pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */ 71*a47a12beSStefan Roese debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10); 72*a47a12beSStefan Roese #endif 73*a47a12beSStefan Roese #ifdef CONFIG_PCIE3 74*a47a12beSStefan Roese pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */ 75*a47a12beSStefan Roese debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11); 76*a47a12beSStefan Roese #endif 77*a47a12beSStefan Roese 78*a47a12beSStefan Roese pic->ctpr=0; /* 40080 clear current task priority register */ 79*a47a12beSStefan Roese #endif 80*a47a12beSStefan Roese 81*a47a12beSStefan Roese return (0); 82*a47a12beSStefan Roese } 83*a47a12beSStefan Roese 84*a47a12beSStefan Roese /* Install and free a interrupt handler. Not implemented yet. */ 85*a47a12beSStefan Roese 86*a47a12beSStefan Roese void 87*a47a12beSStefan Roese irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) 88*a47a12beSStefan Roese { 89*a47a12beSStefan Roese return; 90*a47a12beSStefan Roese } 91*a47a12beSStefan Roese 92*a47a12beSStefan Roese void 93*a47a12beSStefan Roese irq_free_handler(int vec) 94*a47a12beSStefan Roese { 95*a47a12beSStefan Roese return; 96*a47a12beSStefan Roese } 97*a47a12beSStefan Roese 98*a47a12beSStefan Roese void timer_interrupt_cpu(struct pt_regs *regs) 99*a47a12beSStefan Roese { 100*a47a12beSStefan Roese /* PIS is same as DIS, dec interrupt status */ 101*a47a12beSStefan Roese mtspr(SPRN_TSR, TSR_PIS); 102*a47a12beSStefan Roese } 103*a47a12beSStefan Roese 104*a47a12beSStefan Roese #if defined(CONFIG_CMD_IRQ) 105*a47a12beSStefan Roese /* irqinfo - print information about PCI devices,not implemented. */ 106*a47a12beSStefan Roese int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) 107*a47a12beSStefan Roese { 108*a47a12beSStefan Roese return 0; 109*a47a12beSStefan Roese } 110*a47a12beSStefan Roese #endif 111