1 /* 2 * Copyright 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <libfdt.h> 28 #include <fdt_support.h> 29 #include <asm/processor.h> 30 #include <linux/ctype.h> 31 #include <asm/io.h> 32 #ifdef CONFIG_FSL_ESDHC 33 #include <fsl_esdhc.h> 34 #endif 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 extern void ft_qe_setup(void *blob); 39 extern void ft_fixup_num_cores(void *blob); 40 41 #ifdef CONFIG_MP 42 #include "mp.h" 43 44 void ft_fixup_cpu(void *blob, u64 memory_limit) 45 { 46 int off; 47 ulong spin_tbl_addr = get_spin_phys_addr(); 48 u32 bootpg = determine_mp_bootpg(); 49 u32 id = get_my_id(); 50 51 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 52 while (off != -FDT_ERR_NOTFOUND) { 53 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 54 55 if (reg) { 56 if (*reg == id) { 57 fdt_setprop_string(blob, off, "status", "okay"); 58 } else { 59 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; 60 val = cpu_to_fdt32(val); 61 fdt_setprop_string(blob, off, "status", 62 "disabled"); 63 fdt_setprop_string(blob, off, "enable-method", 64 "spin-table"); 65 fdt_setprop(blob, off, "cpu-release-addr", 66 &val, sizeof(val)); 67 } 68 } else { 69 printf ("cpu NULL\n"); 70 } 71 off = fdt_node_offset_by_prop_value(blob, off, 72 "device_type", "cpu", 4); 73 } 74 75 /* Reserve the boot page so OSes dont use it */ 76 if ((u64)bootpg < memory_limit) { 77 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); 78 if (off < 0) 79 printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); 80 } 81 } 82 #endif 83 84 #ifdef CONFIG_SYS_FSL_CPC 85 static inline void ft_fixup_l3cache(void *blob, int off) 86 { 87 u32 line_size, num_ways, size, num_sets; 88 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; 89 u32 cfg0 = in_be32(&cpc->cpccfg0); 90 91 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; 92 num_ways = CPC_CFG0_NUM_WAYS(cfg0); 93 line_size = CPC_CFG0_LINE_SZ(cfg0); 94 num_sets = size / (line_size * num_ways); 95 96 fdt_setprop(blob, off, "cache-unified", NULL, 0); 97 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 98 fdt_setprop_cell(blob, off, "cache-size", size); 99 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 100 fdt_setprop_cell(blob, off, "cache-level", 3); 101 #ifdef CONFIG_SYS_CACHE_STASHING 102 fdt_setprop_cell(blob, off, "cache-stash-id", 1); 103 #endif 104 } 105 #else 106 #define ft_fixup_l3cache(x, y) 107 #endif 108 109 #if defined(CONFIG_L2_CACHE) 110 /* return size in kilobytes */ 111 static inline u32 l2cache_size(void) 112 { 113 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 114 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; 115 u32 ver = SVR_SOC_VER(get_svr()); 116 117 switch (l2siz_field) { 118 case 0x0: 119 break; 120 case 0x1: 121 if (ver == SVR_8540 || ver == SVR_8560 || 122 ver == SVR_8541 || ver == SVR_8541_E || 123 ver == SVR_8555 || ver == SVR_8555_E) 124 return 128; 125 else 126 return 256; 127 break; 128 case 0x2: 129 if (ver == SVR_8540 || ver == SVR_8560 || 130 ver == SVR_8541 || ver == SVR_8541_E || 131 ver == SVR_8555 || ver == SVR_8555_E) 132 return 256; 133 else 134 return 512; 135 break; 136 case 0x3: 137 return 1024; 138 break; 139 } 140 141 return 0; 142 } 143 144 static inline void ft_fixup_l2cache(void *blob) 145 { 146 int len, off; 147 u32 *ph; 148 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); 149 char compat_buf[38]; 150 151 const u32 line_size = 32; 152 const u32 num_ways = 8; 153 const u32 size = l2cache_size() * 1024; 154 const u32 num_sets = size / (line_size * num_ways); 155 156 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 157 if (off < 0) { 158 debug("no cpu node fount\n"); 159 return; 160 } 161 162 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 163 164 if (ph == NULL) { 165 debug("no next-level-cache property\n"); 166 return ; 167 } 168 169 off = fdt_node_offset_by_phandle(blob, *ph); 170 if (off < 0) { 171 printf("%s: %s\n", __func__, fdt_strerror(off)); 172 return ; 173 } 174 175 if (cpu) { 176 if (isdigit(cpu->name[0])) 177 len = sprintf(compat_buf, 178 "fsl,mpc%s-l2-cache-controller", cpu->name); 179 else 180 len = sprintf(compat_buf, 181 "fsl,%c%s-l2-cache-controller", 182 tolower(cpu->name[0]), cpu->name + 1); 183 184 sprintf(&compat_buf[len + 1], "cache"); 185 } 186 fdt_setprop(blob, off, "cache-unified", NULL, 0); 187 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 188 fdt_setprop_cell(blob, off, "cache-size", size); 189 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 190 fdt_setprop_cell(blob, off, "cache-level", 2); 191 fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf)); 192 193 /* we dont bother w/L3 since no platform of this type has one */ 194 } 195 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 196 static inline void ft_fixup_l2cache(void *blob) 197 { 198 int off, l2_off, l3_off = -1; 199 u32 *ph; 200 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 201 u32 size, line_size, num_ways, num_sets; 202 203 size = (l2cfg0 & 0x3fff) * 64 * 1024; 204 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; 205 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; 206 num_sets = size / (line_size * num_ways); 207 208 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 209 210 while (off != -FDT_ERR_NOTFOUND) { 211 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 212 213 if (ph == NULL) { 214 debug("no next-level-cache property\n"); 215 goto next; 216 } 217 218 l2_off = fdt_node_offset_by_phandle(blob, *ph); 219 if (l2_off < 0) { 220 printf("%s: %s\n", __func__, fdt_strerror(off)); 221 goto next; 222 } 223 224 #ifdef CONFIG_SYS_CACHE_STASHING 225 { 226 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 227 if (reg) 228 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 229 (*reg * 2) + 32 + 1); 230 } 231 #endif 232 233 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); 234 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); 235 fdt_setprop_cell(blob, l2_off, "cache-size", size); 236 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); 237 fdt_setprop_cell(blob, l2_off, "cache-level", 2); 238 fdt_setprop(blob, l2_off, "compatible", "cache", 6); 239 240 if (l3_off < 0) { 241 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); 242 243 if (ph == NULL) { 244 debug("no next-level-cache property\n"); 245 goto next; 246 } 247 l3_off = *ph; 248 } 249 next: 250 off = fdt_node_offset_by_prop_value(blob, off, 251 "device_type", "cpu", 4); 252 } 253 if (l3_off > 0) { 254 l3_off = fdt_node_offset_by_phandle(blob, l3_off); 255 if (l3_off < 0) { 256 printf("%s: %s\n", __func__, fdt_strerror(off)); 257 return ; 258 } 259 ft_fixup_l3cache(blob, l3_off); 260 } 261 } 262 #else 263 #define ft_fixup_l2cache(x) 264 #endif 265 266 static inline void ft_fixup_cache(void *blob) 267 { 268 int off; 269 270 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 271 272 while (off != -FDT_ERR_NOTFOUND) { 273 u32 l1cfg0 = mfspr(SPRN_L1CFG0); 274 u32 l1cfg1 = mfspr(SPRN_L1CFG1); 275 u32 isize, iline_size, inum_sets, inum_ways; 276 u32 dsize, dline_size, dnum_sets, dnum_ways; 277 278 /* d-side config */ 279 dsize = (l1cfg0 & 0x7ff) * 1024; 280 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; 281 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; 282 dnum_sets = dsize / (dline_size * dnum_ways); 283 284 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); 285 fdt_setprop_cell(blob, off, "d-cache-size", dsize); 286 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); 287 288 #ifdef CONFIG_SYS_CACHE_STASHING 289 { 290 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 291 if (reg) 292 fdt_setprop_cell(blob, off, "cache-stash-id", 293 (*reg * 2) + 32 + 0); 294 } 295 #endif 296 297 /* i-side config */ 298 isize = (l1cfg1 & 0x7ff) * 1024; 299 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; 300 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; 301 inum_sets = isize / (iline_size * inum_ways); 302 303 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); 304 fdt_setprop_cell(blob, off, "i-cache-size", isize); 305 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); 306 307 off = fdt_node_offset_by_prop_value(blob, off, 308 "device_type", "cpu", 4); 309 } 310 311 ft_fixup_l2cache(blob); 312 } 313 314 315 void fdt_add_enet_stashing(void *fdt) 316 { 317 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); 318 319 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); 320 321 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); 322 } 323 324 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) 325 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, 326 unsigned long freq) 327 { 328 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; 329 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); 330 331 if (off >= 0) { 332 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); 333 if (off > 0) 334 printf("WARNING enable to set clock-frequency " 335 "for %s: %s\n", compat, fdt_strerror(off)); 336 } 337 } 338 339 static void ft_fixup_dpaa_clks(void *blob) 340 { 341 sys_info_t sysinfo; 342 343 get_sys_info(&sysinfo); 344 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, 345 sysinfo.freqFMan[0]); 346 347 #if (CONFIG_SYS_NUM_FMAN == 2) 348 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, 349 sysinfo.freqFMan[1]); 350 #endif 351 352 #ifdef CONFIG_SYS_DPAA_PME 353 do_fixup_by_compat_u32(blob, "fsl,pme", 354 "clock-frequency", sysinfo.freqPME, 1); 355 #endif 356 } 357 #else 358 #define ft_fixup_dpaa_clks(x) 359 #endif 360 361 #ifdef CONFIG_QE 362 static void ft_fixup_qe_snum(void *blob) 363 { 364 unsigned int svr; 365 366 svr = mfspr(SPRN_SVR); 367 if (SVR_SOC_VER(svr) == SVR_8569_E) { 368 if(IS_SVR_REV(svr, 1, 0)) 369 do_fixup_by_compat_u32(blob, "fsl,qe", 370 "fsl,qe-num-snums", 46, 1); 371 else 372 do_fixup_by_compat_u32(blob, "fsl,qe", 373 "fsl,qe-num-snums", 76, 1); 374 } 375 } 376 #endif 377 378 void ft_cpu_setup(void *blob, bd_t *bd) 379 { 380 int off; 381 int val; 382 sys_info_t sysinfo; 383 384 /* delete crypto node if not on an E-processor */ 385 if (!IS_E_PROCESSOR(get_svr())) 386 fdt_fixup_crypto_node(blob, 0); 387 388 fdt_fixup_ethernet(blob); 389 390 fdt_add_enet_stashing(blob); 391 392 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 393 "timebase-frequency", get_tbclk(), 1); 394 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 395 "bus-frequency", bd->bi_busfreq, 1); 396 get_sys_info(&sysinfo); 397 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 398 while (off != -FDT_ERR_NOTFOUND) { 399 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 400 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]); 401 fdt_setprop(blob, off, "clock-frequency", &val, 4); 402 off = fdt_node_offset_by_prop_value(blob, off, "device_type", 403 "cpu", 4); 404 } 405 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 406 "bus-frequency", bd->bi_busfreq, 1); 407 408 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", 409 "bus-frequency", gd->lbc_clk, 1); 410 do_fixup_by_compat_u32(blob, "fsl,elbc", 411 "bus-frequency", gd->lbc_clk, 1); 412 #ifdef CONFIG_QE 413 ft_qe_setup(blob); 414 ft_fixup_qe_snum(blob); 415 #endif 416 417 #ifdef CONFIG_SYS_NS16550 418 do_fixup_by_compat_u32(blob, "ns16550", 419 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 420 #endif 421 422 #ifdef CONFIG_CPM2 423 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", 424 "current-speed", bd->bi_baudrate, 1); 425 426 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", 427 "clock-frequency", bd->bi_brgfreq, 1); 428 #endif 429 430 #ifdef CONFIG_FSL_CORENET 431 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", 432 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 433 #endif 434 435 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); 436 437 #ifdef CONFIG_MP 438 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); 439 ft_fixup_num_cores(blob); 440 #endif 441 442 ft_fixup_cache(blob); 443 444 #if defined(CONFIG_FSL_ESDHC) 445 fdt_fixup_esdhc(blob, bd); 446 #endif 447 448 ft_fixup_dpaa_clks(blob); 449 } 450