1 /* 2 * Copyright 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <sata.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_law.h> 37 #include <asm/fsl_serdes.h> 38 #include "mp.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #ifdef CONFIG_QE 43 extern qe_iop_conf_t qe_iop_conf_tab[]; 44 extern void qe_config_iopin(u8 port, u8 pin, int dir, 45 int open_drain, int assign); 46 extern void qe_init(uint qe_base); 47 extern void qe_reset(void); 48 49 static void config_qe_ioports(void) 50 { 51 u8 port, pin; 52 int dir, open_drain, assign; 53 int i; 54 55 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 56 port = qe_iop_conf_tab[i].port; 57 pin = qe_iop_conf_tab[i].pin; 58 dir = qe_iop_conf_tab[i].dir; 59 open_drain = qe_iop_conf_tab[i].open_drain; 60 assign = qe_iop_conf_tab[i].assign; 61 qe_config_iopin(port, pin, dir, open_drain, assign); 62 } 63 } 64 #endif 65 66 #ifdef CONFIG_CPM2 67 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 68 { 69 int portnum; 70 71 for (portnum = 0; portnum < 4; portnum++) { 72 uint pmsk = 0, 73 ppar = 0, 74 psor = 0, 75 pdir = 0, 76 podr = 0, 77 pdat = 0; 78 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 79 iop_conf_t *eiopc = iopc + 32; 80 uint msk = 1; 81 82 /* 83 * NOTE: 84 * index 0 refers to pin 31, 85 * index 31 refers to pin 0 86 */ 87 while (iopc < eiopc) { 88 if (iopc->conf) { 89 pmsk |= msk; 90 if (iopc->ppar) 91 ppar |= msk; 92 if (iopc->psor) 93 psor |= msk; 94 if (iopc->pdir) 95 pdir |= msk; 96 if (iopc->podr) 97 podr |= msk; 98 if (iopc->pdat) 99 pdat |= msk; 100 } 101 102 msk <<= 1; 103 iopc++; 104 } 105 106 if (pmsk != 0) { 107 volatile ioport_t *iop = ioport_addr (cpm, portnum); 108 uint tpmsk = ~pmsk; 109 110 /* 111 * the (somewhat confused) paragraph at the 112 * bottom of page 35-5 warns that there might 113 * be "unknown behaviour" when programming 114 * PSORx and PDIRx, if PPARx = 1, so I 115 * decided this meant I had to disable the 116 * dedicated function first, and enable it 117 * last. 118 */ 119 iop->ppar &= tpmsk; 120 iop->psor = (iop->psor & tpmsk) | psor; 121 iop->podr = (iop->podr & tpmsk) | podr; 122 iop->pdat = (iop->pdat & tpmsk) | pdat; 123 iop->pdir = (iop->pdir & tpmsk) | pdir; 124 iop->ppar |= ppar; 125 } 126 } 127 } 128 #endif 129 130 /* 131 * Breathe some life into the CPU... 132 * 133 * Set up the memory map 134 * initialize a bunch of registers 135 */ 136 137 #ifdef CONFIG_FSL_CORENET 138 static void corenet_tb_init(void) 139 { 140 volatile ccsr_rcpm_t *rcpm = 141 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 142 volatile ccsr_pic_t *pic = 143 (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 144 u32 whoami = in_be32(&pic->whoami); 145 146 /* Enable the timebase register for this core */ 147 out_be32(&rcpm->ctbenrl, (1 << whoami)); 148 } 149 #endif 150 151 void cpu_init_f (void) 152 { 153 extern void m8560_cpm_reset (void); 154 #ifdef CONFIG_MPC8548 155 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 156 uint svr = get_svr(); 157 158 /* 159 * CPU2 errata workaround: A core hang possible while executing 160 * a msync instruction and a snoopable transaction from an I/O 161 * master tagged to make quick forward progress is present. 162 * Fixed in silicon rev 2.1. 163 */ 164 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 165 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 166 #endif 167 168 disable_tlb(14); 169 disable_tlb(15); 170 171 #ifdef CONFIG_CPM2 172 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 173 #endif 174 175 init_early_memctl_regs(); 176 177 #if defined(CONFIG_CPM2) 178 m8560_cpm_reset(); 179 #endif 180 #ifdef CONFIG_QE 181 /* Config QE ioports */ 182 config_qe_ioports(); 183 #endif 184 #if defined(CONFIG_FSL_DMA) 185 dma_init(); 186 #endif 187 #ifdef CONFIG_FSL_CORENET 188 corenet_tb_init(); 189 #endif 190 init_used_tlb_cams(); 191 } 192 193 194 /* 195 * Initialize L2 as cache. 196 * 197 * The newer 8548, etc, parts have twice as much cache, but 198 * use the same bit-encoding as the older 8555, etc, parts. 199 * 200 */ 201 202 int cpu_init_r(void) 203 { 204 #ifdef CONFIG_SYS_LBC_LCRR 205 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 206 #endif 207 208 puts ("L2: "); 209 210 #if defined(CONFIG_L2_CACHE) 211 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 212 volatile uint cache_ctl; 213 uint svr, ver; 214 uint l2srbar; 215 u32 l2siz_field; 216 217 svr = get_svr(); 218 ver = SVR_SOC_VER(svr); 219 220 asm("msync;isync"); 221 cache_ctl = l2cache->l2ctl; 222 223 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 224 if (cache_ctl & MPC85xx_L2CTL_L2E) { 225 /* Clear L2 SRAM memory-mapped base address */ 226 out_be32(&l2cache->l2srbar0, 0x0); 227 out_be32(&l2cache->l2srbar1, 0x0); 228 229 /* set MBECCDIS=0, SBECCDIS=0 */ 230 clrbits_be32(&l2cache->l2errdis, 231 (MPC85xx_L2ERRDIS_MBECC | 232 MPC85xx_L2ERRDIS_SBECC)); 233 234 /* set L2E=0, L2SRAM=0 */ 235 clrbits_be32(&l2cache->l2ctl, 236 (MPC85xx_L2CTL_L2E | 237 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 238 } 239 #endif 240 241 l2siz_field = (cache_ctl >> 28) & 0x3; 242 243 switch (l2siz_field) { 244 case 0x0: 245 printf(" unknown size (0x%08x)\n", cache_ctl); 246 return -1; 247 break; 248 case 0x1: 249 if (ver == SVR_8540 || ver == SVR_8560 || 250 ver == SVR_8541 || ver == SVR_8541_E || 251 ver == SVR_8555 || ver == SVR_8555_E) { 252 puts("128 KB "); 253 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 254 cache_ctl = 0xc4000000; 255 } else { 256 puts("256 KB "); 257 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 258 } 259 break; 260 case 0x2: 261 if (ver == SVR_8540 || ver == SVR_8560 || 262 ver == SVR_8541 || ver == SVR_8541_E || 263 ver == SVR_8555 || ver == SVR_8555_E) { 264 puts("256 KB "); 265 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 266 cache_ctl = 0xc8000000; 267 } else { 268 puts ("512 KB "); 269 /* set L2E=1, L2I=1, & L2SRAM=0 */ 270 cache_ctl = 0xc0000000; 271 } 272 break; 273 case 0x3: 274 puts("1024 KB "); 275 /* set L2E=1, L2I=1, & L2SRAM=0 */ 276 cache_ctl = 0xc0000000; 277 break; 278 } 279 280 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 281 puts("already enabled"); 282 l2srbar = l2cache->l2srbar0; 283 #ifdef CONFIG_SYS_INIT_L2_ADDR 284 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 285 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 286 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 287 l2cache->l2srbar0 = l2srbar; 288 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 289 } 290 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 291 puts("\n"); 292 } else { 293 asm("msync;isync"); 294 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 295 asm("msync;isync"); 296 puts("enabled\n"); 297 } 298 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 299 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 300 301 /* invalidate the L2 cache */ 302 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 303 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 304 ; 305 306 #ifdef CONFIG_SYS_CACHE_STASHING 307 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 308 mtspr(SPRN_L2CSR1, (32 + 1)); 309 #endif 310 311 /* enable the cache */ 312 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 313 314 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 315 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 316 ; 317 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 318 } 319 #else 320 puts("disabled\n"); 321 #endif 322 #ifdef CONFIG_QE 323 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 324 qe_init(qe_base); 325 qe_reset(); 326 #endif 327 328 #if defined(CONFIG_SYS_HAS_SERDES) 329 /* needs to be in ram since code uses global static vars */ 330 fsl_serdes_init(); 331 #endif 332 333 #if defined(CONFIG_MP) 334 setup_mp(); 335 #endif 336 337 #ifdef CONFIG_SYS_LBC_LCRR 338 /* 339 * Modify the CLKDIV field of LCRR register to improve the writing 340 * speed for NOR flash. 341 */ 342 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 343 __raw_readl(&lbc->lcrr); 344 isync(); 345 #endif 346 347 return 0; 348 } 349 350 extern void setup_ivors(void); 351 352 void arch_preboot_os(void) 353 { 354 u32 msr; 355 356 /* 357 * We are changing interrupt offsets and are about to boot the OS so 358 * we need to make sure we disable all async interrupts. EE is already 359 * disabled by the time we get called. 360 */ 361 msr = mfmsr(); 362 msr &= ~(MSR_ME|MSR_CE|MSR_DE); 363 mtmsr(msr); 364 365 setup_ivors(); 366 } 367 368 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 369 int sata_initialize(void) 370 { 371 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 372 return __sata_initialize(); 373 374 return 1; 375 } 376 #endif 377