1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <sata.h> 34 #include <asm/io.h> 35 #include <asm/cache.h> 36 #include <asm/mmu.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_serdes.h> 39 #include "mp.h" 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 extern void srio_init(void); 44 45 #ifdef CONFIG_QE 46 extern qe_iop_conf_t qe_iop_conf_tab[]; 47 extern void qe_config_iopin(u8 port, u8 pin, int dir, 48 int open_drain, int assign); 49 extern void qe_init(uint qe_base); 50 extern void qe_reset(void); 51 52 static void config_qe_ioports(void) 53 { 54 u8 port, pin; 55 int dir, open_drain, assign; 56 int i; 57 58 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 59 port = qe_iop_conf_tab[i].port; 60 pin = qe_iop_conf_tab[i].pin; 61 dir = qe_iop_conf_tab[i].dir; 62 open_drain = qe_iop_conf_tab[i].open_drain; 63 assign = qe_iop_conf_tab[i].assign; 64 qe_config_iopin(port, pin, dir, open_drain, assign); 65 } 66 } 67 #endif 68 69 #ifdef CONFIG_CPM2 70 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 71 { 72 int portnum; 73 74 for (portnum = 0; portnum < 4; portnum++) { 75 uint pmsk = 0, 76 ppar = 0, 77 psor = 0, 78 pdir = 0, 79 podr = 0, 80 pdat = 0; 81 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 82 iop_conf_t *eiopc = iopc + 32; 83 uint msk = 1; 84 85 /* 86 * NOTE: 87 * index 0 refers to pin 31, 88 * index 31 refers to pin 0 89 */ 90 while (iopc < eiopc) { 91 if (iopc->conf) { 92 pmsk |= msk; 93 if (iopc->ppar) 94 ppar |= msk; 95 if (iopc->psor) 96 psor |= msk; 97 if (iopc->pdir) 98 pdir |= msk; 99 if (iopc->podr) 100 podr |= msk; 101 if (iopc->pdat) 102 pdat |= msk; 103 } 104 105 msk <<= 1; 106 iopc++; 107 } 108 109 if (pmsk != 0) { 110 volatile ioport_t *iop = ioport_addr (cpm, portnum); 111 uint tpmsk = ~pmsk; 112 113 /* 114 * the (somewhat confused) paragraph at the 115 * bottom of page 35-5 warns that there might 116 * be "unknown behaviour" when programming 117 * PSORx and PDIRx, if PPARx = 1, so I 118 * decided this meant I had to disable the 119 * dedicated function first, and enable it 120 * last. 121 */ 122 iop->ppar &= tpmsk; 123 iop->psor = (iop->psor & tpmsk) | psor; 124 iop->podr = (iop->podr & tpmsk) | podr; 125 iop->pdat = (iop->pdat & tpmsk) | pdat; 126 iop->pdir = (iop->pdir & tpmsk) | pdir; 127 iop->ppar |= ppar; 128 } 129 } 130 } 131 #endif 132 133 #ifdef CONFIG_SYS_FSL_CPC 134 static void enable_cpc(void) 135 { 136 int i; 137 u32 size = 0; 138 139 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 140 141 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 142 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 143 size += CPC_CFG0_SZ_K(cpccfg0); 144 145 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 146 /* Read back to sync write */ 147 in_be32(&cpc->cpccsr0); 148 149 } 150 151 printf("Corenet Platform Cache: %d KB enabled\n", size); 152 } 153 154 void invalidate_cpc(void) 155 { 156 int i; 157 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 158 159 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 160 /* Flash invalidate the CPC and clear all the locks */ 161 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 162 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 163 ; 164 } 165 } 166 #else 167 #define enable_cpc() 168 #define invalidate_cpc() 169 #endif /* CONFIG_SYS_FSL_CPC */ 170 171 /* 172 * Breathe some life into the CPU... 173 * 174 * Set up the memory map 175 * initialize a bunch of registers 176 */ 177 178 #ifdef CONFIG_FSL_CORENET 179 static void corenet_tb_init(void) 180 { 181 volatile ccsr_rcpm_t *rcpm = 182 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 183 volatile ccsr_pic_t *pic = 184 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 185 u32 whoami = in_be32(&pic->whoami); 186 187 /* Enable the timebase register for this core */ 188 out_be32(&rcpm->ctbenrl, (1 << whoami)); 189 } 190 #endif 191 192 void cpu_init_f (void) 193 { 194 extern void m8560_cpm_reset (void); 195 #ifdef CONFIG_MPC8548 196 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 197 uint svr = get_svr(); 198 199 /* 200 * CPU2 errata workaround: A core hang possible while executing 201 * a msync instruction and a snoopable transaction from an I/O 202 * master tagged to make quick forward progress is present. 203 * Fixed in silicon rev 2.1. 204 */ 205 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 206 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 207 #endif 208 209 disable_tlb(14); 210 disable_tlb(15); 211 212 #ifdef CONFIG_CPM2 213 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 214 #endif 215 216 init_early_memctl_regs(); 217 218 #if defined(CONFIG_CPM2) 219 m8560_cpm_reset(); 220 #endif 221 #ifdef CONFIG_QE 222 /* Config QE ioports */ 223 config_qe_ioports(); 224 #endif 225 #if defined(CONFIG_FSL_DMA) 226 dma_init(); 227 #endif 228 #ifdef CONFIG_FSL_CORENET 229 corenet_tb_init(); 230 #endif 231 init_used_tlb_cams(); 232 233 /* Invalidate the CPC before DDR gets enabled */ 234 invalidate_cpc(); 235 } 236 237 /* Implement a dummy function for those platforms w/o SERDES */ 238 static void __fsl_serdes__init(void) 239 { 240 return ; 241 } 242 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 243 244 /* 245 * Initialize L2 as cache. 246 * 247 * The newer 8548, etc, parts have twice as much cache, but 248 * use the same bit-encoding as the older 8555, etc, parts. 249 * 250 */ 251 int cpu_init_r(void) 252 { 253 #ifdef CONFIG_SYS_LBC_LCRR 254 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 255 #endif 256 257 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) 258 flush_dcache(); 259 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 260 sync(); 261 #endif 262 263 puts ("L2: "); 264 265 #if defined(CONFIG_L2_CACHE) 266 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 267 volatile uint cache_ctl; 268 uint svr, ver; 269 uint l2srbar; 270 u32 l2siz_field; 271 272 svr = get_svr(); 273 ver = SVR_SOC_VER(svr); 274 275 asm("msync;isync"); 276 cache_ctl = l2cache->l2ctl; 277 278 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 279 if (cache_ctl & MPC85xx_L2CTL_L2E) { 280 /* Clear L2 SRAM memory-mapped base address */ 281 out_be32(&l2cache->l2srbar0, 0x0); 282 out_be32(&l2cache->l2srbar1, 0x0); 283 284 /* set MBECCDIS=0, SBECCDIS=0 */ 285 clrbits_be32(&l2cache->l2errdis, 286 (MPC85xx_L2ERRDIS_MBECC | 287 MPC85xx_L2ERRDIS_SBECC)); 288 289 /* set L2E=0, L2SRAM=0 */ 290 clrbits_be32(&l2cache->l2ctl, 291 (MPC85xx_L2CTL_L2E | 292 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 293 } 294 #endif 295 296 l2siz_field = (cache_ctl >> 28) & 0x3; 297 298 switch (l2siz_field) { 299 case 0x0: 300 printf(" unknown size (0x%08x)\n", cache_ctl); 301 return -1; 302 break; 303 case 0x1: 304 if (ver == SVR_8540 || ver == SVR_8560 || 305 ver == SVR_8541 || ver == SVR_8541_E || 306 ver == SVR_8555 || ver == SVR_8555_E) { 307 puts("128 KB "); 308 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 309 cache_ctl = 0xc4000000; 310 } else { 311 puts("256 KB "); 312 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 313 } 314 break; 315 case 0x2: 316 if (ver == SVR_8540 || ver == SVR_8560 || 317 ver == SVR_8541 || ver == SVR_8541_E || 318 ver == SVR_8555 || ver == SVR_8555_E) { 319 puts("256 KB "); 320 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 321 cache_ctl = 0xc8000000; 322 } else { 323 puts ("512 KB "); 324 /* set L2E=1, L2I=1, & L2SRAM=0 */ 325 cache_ctl = 0xc0000000; 326 } 327 break; 328 case 0x3: 329 puts("1024 KB "); 330 /* set L2E=1, L2I=1, & L2SRAM=0 */ 331 cache_ctl = 0xc0000000; 332 break; 333 } 334 335 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 336 puts("already enabled"); 337 l2srbar = l2cache->l2srbar0; 338 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 339 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 340 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 341 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 342 l2cache->l2srbar0 = l2srbar; 343 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 344 } 345 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 346 puts("\n"); 347 } else { 348 asm("msync;isync"); 349 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 350 asm("msync;isync"); 351 puts("enabled\n"); 352 } 353 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 354 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 355 356 /* invalidate the L2 cache */ 357 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 358 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 359 ; 360 361 #ifdef CONFIG_SYS_CACHE_STASHING 362 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 363 mtspr(SPRN_L2CSR1, (32 + 1)); 364 #endif 365 366 /* enable the cache */ 367 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 368 369 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 370 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 371 ; 372 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 373 } 374 #else 375 puts("disabled\n"); 376 #endif 377 378 enable_cpc(); 379 380 #ifdef CONFIG_QE 381 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 382 qe_init(qe_base); 383 qe_reset(); 384 #endif 385 386 /* needs to be in ram since code uses global static vars */ 387 fsl_serdes_init(); 388 389 #ifdef CONFIG_SYS_SRIO 390 srio_init(); 391 #endif 392 393 #if defined(CONFIG_MP) 394 setup_mp(); 395 #endif 396 397 #ifdef CONFIG_SYS_LBC_LCRR 398 /* 399 * Modify the CLKDIV field of LCRR register to improve the writing 400 * speed for NOR flash. 401 */ 402 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 403 __raw_readl(&lbc->lcrr); 404 isync(); 405 #endif 406 407 return 0; 408 } 409 410 extern void setup_ivors(void); 411 412 void arch_preboot_os(void) 413 { 414 u32 msr; 415 416 /* 417 * We are changing interrupt offsets and are about to boot the OS so 418 * we need to make sure we disable all async interrupts. EE is already 419 * disabled by the time we get called. 420 */ 421 msr = mfmsr(); 422 msr &= ~(MSR_ME|MSR_CE|MSR_DE); 423 mtmsr(msr); 424 425 setup_ivors(); 426 } 427 428 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 429 int sata_initialize(void) 430 { 431 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 432 return __sata_initialize(); 433 434 return 1; 435 } 436 #endif 437