1 /* 2 * Copyright 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <sata.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_law.h> 37 #include <asm/fsl_serdes.h> 38 #include "mp.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #ifdef CONFIG_QE 43 extern qe_iop_conf_t qe_iop_conf_tab[]; 44 extern void qe_config_iopin(u8 port, u8 pin, int dir, 45 int open_drain, int assign); 46 extern void qe_init(uint qe_base); 47 extern void qe_reset(void); 48 49 static void config_qe_ioports(void) 50 { 51 u8 port, pin; 52 int dir, open_drain, assign; 53 int i; 54 55 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 56 port = qe_iop_conf_tab[i].port; 57 pin = qe_iop_conf_tab[i].pin; 58 dir = qe_iop_conf_tab[i].dir; 59 open_drain = qe_iop_conf_tab[i].open_drain; 60 assign = qe_iop_conf_tab[i].assign; 61 qe_config_iopin(port, pin, dir, open_drain, assign); 62 } 63 } 64 #endif 65 66 #ifdef CONFIG_CPM2 67 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 68 { 69 int portnum; 70 71 for (portnum = 0; portnum < 4; portnum++) { 72 uint pmsk = 0, 73 ppar = 0, 74 psor = 0, 75 pdir = 0, 76 podr = 0, 77 pdat = 0; 78 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 79 iop_conf_t *eiopc = iopc + 32; 80 uint msk = 1; 81 82 /* 83 * NOTE: 84 * index 0 refers to pin 31, 85 * index 31 refers to pin 0 86 */ 87 while (iopc < eiopc) { 88 if (iopc->conf) { 89 pmsk |= msk; 90 if (iopc->ppar) 91 ppar |= msk; 92 if (iopc->psor) 93 psor |= msk; 94 if (iopc->pdir) 95 pdir |= msk; 96 if (iopc->podr) 97 podr |= msk; 98 if (iopc->pdat) 99 pdat |= msk; 100 } 101 102 msk <<= 1; 103 iopc++; 104 } 105 106 if (pmsk != 0) { 107 volatile ioport_t *iop = ioport_addr (cpm, portnum); 108 uint tpmsk = ~pmsk; 109 110 /* 111 * the (somewhat confused) paragraph at the 112 * bottom of page 35-5 warns that there might 113 * be "unknown behaviour" when programming 114 * PSORx and PDIRx, if PPARx = 1, so I 115 * decided this meant I had to disable the 116 * dedicated function first, and enable it 117 * last. 118 */ 119 iop->ppar &= tpmsk; 120 iop->psor = (iop->psor & tpmsk) | psor; 121 iop->podr = (iop->podr & tpmsk) | podr; 122 iop->pdat = (iop->pdat & tpmsk) | pdat; 123 iop->pdir = (iop->pdir & tpmsk) | pdir; 124 iop->ppar |= ppar; 125 } 126 } 127 } 128 #endif 129 130 #ifdef CONFIG_SYS_FSL_CPC 131 static void enable_cpc(void) 132 { 133 int i; 134 u32 size = 0; 135 136 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 137 138 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 139 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 140 size += CPC_CFG0_SZ_K(cpccfg0); 141 142 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 143 /* Read back to sync write */ 144 in_be32(&cpc->cpccsr0); 145 146 } 147 148 printf("Corenet Platform Cache: %d KB enabled\n", size); 149 } 150 151 void invalidate_cpc(void) 152 { 153 int i; 154 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 155 156 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 157 /* Flash invalidate the CPC and clear all the locks */ 158 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 159 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 160 ; 161 } 162 } 163 #else 164 #define enable_cpc() 165 #define invalidate_cpc() 166 #endif /* CONFIG_SYS_FSL_CPC */ 167 168 /* 169 * Breathe some life into the CPU... 170 * 171 * Set up the memory map 172 * initialize a bunch of registers 173 */ 174 175 #ifdef CONFIG_FSL_CORENET 176 static void corenet_tb_init(void) 177 { 178 volatile ccsr_rcpm_t *rcpm = 179 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 180 volatile ccsr_pic_t *pic = 181 (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 182 u32 whoami = in_be32(&pic->whoami); 183 184 /* Enable the timebase register for this core */ 185 out_be32(&rcpm->ctbenrl, (1 << whoami)); 186 } 187 #endif 188 189 void cpu_init_f (void) 190 { 191 extern void m8560_cpm_reset (void); 192 #ifdef CONFIG_MPC8548 193 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 194 uint svr = get_svr(); 195 196 /* 197 * CPU2 errata workaround: A core hang possible while executing 198 * a msync instruction and a snoopable transaction from an I/O 199 * master tagged to make quick forward progress is present. 200 * Fixed in silicon rev 2.1. 201 */ 202 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 203 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 204 #endif 205 206 disable_tlb(14); 207 disable_tlb(15); 208 209 #ifdef CONFIG_CPM2 210 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 211 #endif 212 213 init_early_memctl_regs(); 214 215 #if defined(CONFIG_CPM2) 216 m8560_cpm_reset(); 217 #endif 218 #ifdef CONFIG_QE 219 /* Config QE ioports */ 220 config_qe_ioports(); 221 #endif 222 #if defined(CONFIG_FSL_DMA) 223 dma_init(); 224 #endif 225 #ifdef CONFIG_FSL_CORENET 226 corenet_tb_init(); 227 #endif 228 init_used_tlb_cams(); 229 230 /* Invalidate the CPC before DDR gets enabled */ 231 invalidate_cpc(); 232 } 233 234 235 /* 236 * Initialize L2 as cache. 237 * 238 * The newer 8548, etc, parts have twice as much cache, but 239 * use the same bit-encoding as the older 8555, etc, parts. 240 * 241 */ 242 int cpu_init_r(void) 243 { 244 #ifdef CONFIG_SYS_LBC_LCRR 245 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 246 #endif 247 248 puts ("L2: "); 249 250 #if defined(CONFIG_L2_CACHE) 251 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 252 volatile uint cache_ctl; 253 uint svr, ver; 254 uint l2srbar; 255 u32 l2siz_field; 256 257 svr = get_svr(); 258 ver = SVR_SOC_VER(svr); 259 260 asm("msync;isync"); 261 cache_ctl = l2cache->l2ctl; 262 263 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 264 if (cache_ctl & MPC85xx_L2CTL_L2E) { 265 /* Clear L2 SRAM memory-mapped base address */ 266 out_be32(&l2cache->l2srbar0, 0x0); 267 out_be32(&l2cache->l2srbar1, 0x0); 268 269 /* set MBECCDIS=0, SBECCDIS=0 */ 270 clrbits_be32(&l2cache->l2errdis, 271 (MPC85xx_L2ERRDIS_MBECC | 272 MPC85xx_L2ERRDIS_SBECC)); 273 274 /* set L2E=0, L2SRAM=0 */ 275 clrbits_be32(&l2cache->l2ctl, 276 (MPC85xx_L2CTL_L2E | 277 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 278 } 279 #endif 280 281 l2siz_field = (cache_ctl >> 28) & 0x3; 282 283 switch (l2siz_field) { 284 case 0x0: 285 printf(" unknown size (0x%08x)\n", cache_ctl); 286 return -1; 287 break; 288 case 0x1: 289 if (ver == SVR_8540 || ver == SVR_8560 || 290 ver == SVR_8541 || ver == SVR_8541_E || 291 ver == SVR_8555 || ver == SVR_8555_E) { 292 puts("128 KB "); 293 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 294 cache_ctl = 0xc4000000; 295 } else { 296 puts("256 KB "); 297 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 298 } 299 break; 300 case 0x2: 301 if (ver == SVR_8540 || ver == SVR_8560 || 302 ver == SVR_8541 || ver == SVR_8541_E || 303 ver == SVR_8555 || ver == SVR_8555_E) { 304 puts("256 KB "); 305 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 306 cache_ctl = 0xc8000000; 307 } else { 308 puts ("512 KB "); 309 /* set L2E=1, L2I=1, & L2SRAM=0 */ 310 cache_ctl = 0xc0000000; 311 } 312 break; 313 case 0x3: 314 puts("1024 KB "); 315 /* set L2E=1, L2I=1, & L2SRAM=0 */ 316 cache_ctl = 0xc0000000; 317 break; 318 } 319 320 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 321 puts("already enabled"); 322 l2srbar = l2cache->l2srbar0; 323 #ifdef CONFIG_SYS_INIT_L2_ADDR 324 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 325 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 326 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 327 l2cache->l2srbar0 = l2srbar; 328 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 329 } 330 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 331 puts("\n"); 332 } else { 333 asm("msync;isync"); 334 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 335 asm("msync;isync"); 336 puts("enabled\n"); 337 } 338 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 339 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 340 341 /* invalidate the L2 cache */ 342 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 343 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 344 ; 345 346 #ifdef CONFIG_SYS_CACHE_STASHING 347 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 348 mtspr(SPRN_L2CSR1, (32 + 1)); 349 #endif 350 351 /* enable the cache */ 352 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 353 354 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 355 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 356 ; 357 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 358 } 359 #else 360 puts("disabled\n"); 361 #endif 362 363 enable_cpc(); 364 365 #ifdef CONFIG_QE 366 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 367 qe_init(qe_base); 368 qe_reset(); 369 #endif 370 371 #if defined(CONFIG_SYS_HAS_SERDES) 372 /* needs to be in ram since code uses global static vars */ 373 fsl_serdes_init(); 374 #endif 375 376 #if defined(CONFIG_MP) 377 setup_mp(); 378 #endif 379 380 #ifdef CONFIG_SYS_LBC_LCRR 381 /* 382 * Modify the CLKDIV field of LCRR register to improve the writing 383 * speed for NOR flash. 384 */ 385 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 386 __raw_readl(&lbc->lcrr); 387 isync(); 388 #endif 389 390 return 0; 391 } 392 393 extern void setup_ivors(void); 394 395 void arch_preboot_os(void) 396 { 397 u32 msr; 398 399 /* 400 * We are changing interrupt offsets and are about to boot the OS so 401 * we need to make sure we disable all async interrupts. EE is already 402 * disabled by the time we get called. 403 */ 404 msr = mfmsr(); 405 msr &= ~(MSR_ME|MSR_CE|MSR_DE); 406 mtmsr(msr); 407 408 setup_ivors(); 409 } 410 411 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 412 int sata_initialize(void) 413 { 414 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 415 return __sata_initialize(); 416 417 return 1; 418 } 419 #endif 420