1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <asm/fsl_errata.h> 23 #include <asm/fsl_law.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_srio.h> 26 #include <fsl_usb.h> 27 #include <hwconfig.h> 28 #include <linux/compiler.h> 29 #include "mp.h" 30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 31 #include <nand.h> 32 #include <errno.h> 33 #endif 34 35 #include "../../../../drivers/block/fsl_sata.h" 36 #ifdef CONFIG_U_QE 37 #include "../../../../drivers/qe/qe.h" 38 #endif 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 43 /* 44 * For deriving usb clock from 100MHz sysclk, reference divisor is set 45 * to a value of 5, which gives an intermediate value 20(100/5). The 46 * multiplication factor integer is set to 24, which when multiplied to 47 * above intermediate value provides clock for usb ip. 48 */ 49 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) 50 { 51 sys_info_t sysinfo; 52 53 get_sys_info(&sysinfo); 54 if (sysinfo.diff_sysclk == 1) { 55 clrbits_be32(&usb_phy->pllprg[1], 56 CONFIG_SYS_FSL_USB_PLLPRG2_MFI); 57 setbits_be32(&usb_phy->pllprg[1], 58 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | 59 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | 60 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); 61 } 62 } 63 #endif 64 65 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 66 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 67 { 68 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 69 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 70 71 /* Increase Disconnect Threshold by 50mV */ 72 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 73 INC_DCNT_THRESHOLD_50MV; 74 /* Enable programming of USB High speed Disconnect threshold */ 75 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 76 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 77 78 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 79 /* Increase Disconnect Threshold by 50mV */ 80 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 81 INC_DCNT_THRESHOLD_50MV; 82 /* Enable programming of USB High speed Disconnect threshold */ 83 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 84 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 85 #else 86 87 u32 temp = 0; 88 u32 status = in_be32(&usb_phy->status1); 89 90 u32 squelch_prog_rd_0_2 = 91 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 92 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 93 94 u32 squelch_prog_rd_3_5 = 95 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 96 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 97 98 setbits_be32(&usb_phy->config1, 99 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); 100 setbits_be32(&usb_phy->config2, 101 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 102 103 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 104 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 105 106 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 107 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 108 #endif 109 } 110 #endif 111 112 113 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 114 extern qe_iop_conf_t qe_iop_conf_tab[]; 115 extern void qe_config_iopin(u8 port, u8 pin, int dir, 116 int open_drain, int assign); 117 extern void qe_init(uint qe_base); 118 extern void qe_reset(void); 119 120 static void config_qe_ioports(void) 121 { 122 u8 port, pin; 123 int dir, open_drain, assign; 124 int i; 125 126 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 127 port = qe_iop_conf_tab[i].port; 128 pin = qe_iop_conf_tab[i].pin; 129 dir = qe_iop_conf_tab[i].dir; 130 open_drain = qe_iop_conf_tab[i].open_drain; 131 assign = qe_iop_conf_tab[i].assign; 132 qe_config_iopin(port, pin, dir, open_drain, assign); 133 } 134 } 135 #endif 136 137 #ifdef CONFIG_CPM2 138 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 139 { 140 int portnum; 141 142 for (portnum = 0; portnum < 4; portnum++) { 143 uint pmsk = 0, 144 ppar = 0, 145 psor = 0, 146 pdir = 0, 147 podr = 0, 148 pdat = 0; 149 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 150 iop_conf_t *eiopc = iopc + 32; 151 uint msk = 1; 152 153 /* 154 * NOTE: 155 * index 0 refers to pin 31, 156 * index 31 refers to pin 0 157 */ 158 while (iopc < eiopc) { 159 if (iopc->conf) { 160 pmsk |= msk; 161 if (iopc->ppar) 162 ppar |= msk; 163 if (iopc->psor) 164 psor |= msk; 165 if (iopc->pdir) 166 pdir |= msk; 167 if (iopc->podr) 168 podr |= msk; 169 if (iopc->pdat) 170 pdat |= msk; 171 } 172 173 msk <<= 1; 174 iopc++; 175 } 176 177 if (pmsk != 0) { 178 volatile ioport_t *iop = ioport_addr (cpm, portnum); 179 uint tpmsk = ~pmsk; 180 181 /* 182 * the (somewhat confused) paragraph at the 183 * bottom of page 35-5 warns that there might 184 * be "unknown behaviour" when programming 185 * PSORx and PDIRx, if PPARx = 1, so I 186 * decided this meant I had to disable the 187 * dedicated function first, and enable it 188 * last. 189 */ 190 iop->ppar &= tpmsk; 191 iop->psor = (iop->psor & tpmsk) | psor; 192 iop->podr = (iop->podr & tpmsk) | podr; 193 iop->pdat = (iop->pdat & tpmsk) | pdat; 194 iop->pdir = (iop->pdir & tpmsk) | pdir; 195 iop->ppar |= ppar; 196 } 197 } 198 } 199 #endif 200 201 #ifdef CONFIG_SYS_FSL_CPC 202 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 203 static void disable_cpc_sram(void) 204 { 205 int i; 206 207 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 208 209 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 210 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 211 /* find and disable LAW of SRAM */ 212 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 213 214 if (law.index == -1) { 215 printf("\nFatal error happened\n"); 216 return; 217 } 218 disable_law(law.index); 219 220 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 221 out_be32(&cpc->cpccsr0, 0); 222 out_be32(&cpc->cpcsrcr0, 0); 223 } 224 } 225 } 226 #endif 227 228 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 229 #ifdef CONFIG_POST 230 #error POST memory test cannot be enabled with TDM 231 #endif 232 static void enable_tdm_law(void) 233 { 234 int ret; 235 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 236 int tdm_hwconfig_enabled = 0; 237 238 /* 239 * Extract hwconfig from environment since environment 240 * is not setup properly yet. Search for tdm entry in 241 * hwconfig. 242 */ 243 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 244 if (ret > 0) { 245 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 246 /* If tdm is defined in hwconfig, set law for tdm workaround */ 247 if (tdm_hwconfig_enabled) 248 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, 249 LAW_TRGT_IF_CCSR); 250 } 251 } 252 #endif 253 254 static void enable_cpc(void) 255 { 256 int i; 257 u32 size = 0; 258 259 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 260 261 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 262 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 263 size += CPC_CFG0_SZ_K(cpccfg0); 264 265 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 266 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 267 #endif 268 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 269 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 270 #endif 271 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 272 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 273 #endif 274 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 275 if (has_erratum_a006379()) { 276 setbits_be32(&cpc->cpchdbcr0, 277 CPC_HDBCR0_SPLRU_LEVEL_EN); 278 } 279 #endif 280 281 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 282 /* Read back to sync write */ 283 in_be32(&cpc->cpccsr0); 284 285 } 286 287 puts("Corenet Platform Cache: "); 288 print_size(size * 1024, " enabled\n"); 289 } 290 291 static void invalidate_cpc(void) 292 { 293 int i; 294 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 295 296 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 297 /* skip CPC when it used as all SRAM */ 298 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 299 continue; 300 /* Flash invalidate the CPC and clear all the locks */ 301 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 302 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 303 ; 304 } 305 } 306 #else 307 #define enable_cpc() 308 #define invalidate_cpc() 309 #endif /* CONFIG_SYS_FSL_CPC */ 310 311 /* 312 * Breathe some life into the CPU... 313 * 314 * Set up the memory map 315 * initialize a bunch of registers 316 */ 317 318 #ifdef CONFIG_FSL_CORENET 319 static void corenet_tb_init(void) 320 { 321 volatile ccsr_rcpm_t *rcpm = 322 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 323 volatile ccsr_pic_t *pic = 324 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 325 u32 whoami = in_be32(&pic->whoami); 326 327 /* Enable the timebase register for this core */ 328 out_be32(&rcpm->ctbenrl, (1 << whoami)); 329 } 330 #endif 331 332 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 333 void fsl_erratum_a007212_workaround(void) 334 { 335 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 336 u32 ddr_pll_ratio; 337 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); 338 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); 339 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); 340 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 341 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); 342 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); 343 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 344 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); 345 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); 346 #endif 347 #endif 348 /* 349 * Even this workaround applies to selected version of SoCs, it is 350 * safe to apply to all versions, with the limitation of odd ratios. 351 * If RCW has disabled DDR PLL, we have to apply this workaround, 352 * otherwise DDR will not work. 353 */ 354 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 355 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & 356 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 357 /* check if RCW sets ratio to 0, required by this workaround */ 358 if (ddr_pll_ratio != 0) 359 return; 360 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 361 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 362 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 363 /* check if reserved bits have the desired ratio */ 364 if (ddr_pll_ratio == 0) { 365 printf("Error: Unknown DDR PLL ratio!\n"); 366 return; 367 } 368 ddr_pll_ratio >>= 1; 369 370 setbits_be32(plldadcr1, 0x02000001); 371 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 372 setbits_be32(plldadcr2, 0x02000001); 373 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 374 setbits_be32(plldadcr3, 0x02000001); 375 #endif 376 #endif 377 setbits_be32(dpdovrcr4, 0xe0000000); 378 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); 379 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 380 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); 381 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 382 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); 383 #endif 384 #endif 385 udelay(100); 386 clrbits_be32(plldadcr1, 0x02000001); 387 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 388 clrbits_be32(plldadcr2, 0x02000001); 389 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 390 clrbits_be32(plldadcr3, 0x02000001); 391 #endif 392 #endif 393 clrbits_be32(dpdovrcr4, 0xe0000000); 394 } 395 #endif 396 397 ulong cpu_init_f(void) 398 { 399 ulong flag = 0; 400 extern void m8560_cpm_reset (void); 401 #ifdef CONFIG_SYS_DCSRBAR_PHYS 402 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 403 #endif 404 #if defined(CONFIG_SECURE_BOOT) 405 struct law_entry law; 406 #endif 407 #ifdef CONFIG_MPC8548 408 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 409 uint svr = get_svr(); 410 411 /* 412 * CPU2 errata workaround: A core hang possible while executing 413 * a msync instruction and a snoopable transaction from an I/O 414 * master tagged to make quick forward progress is present. 415 * Fixed in silicon rev 2.1. 416 */ 417 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 418 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 419 #endif 420 421 disable_tlb(14); 422 disable_tlb(15); 423 424 #if defined(CONFIG_SECURE_BOOT) 425 /* Disable the LAW created for NOR flash by the PBI commands */ 426 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 427 if (law.index != -1) 428 disable_law(law.index); 429 430 #if defined(CONFIG_SYS_CPC_REINIT_F) 431 disable_cpc_sram(); 432 #endif 433 #endif 434 435 #ifdef CONFIG_CPM2 436 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 437 #endif 438 439 init_early_memctl_regs(); 440 441 #if defined(CONFIG_CPM2) 442 m8560_cpm_reset(); 443 #endif 444 445 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 446 /* Config QE ioports */ 447 config_qe_ioports(); 448 #endif 449 450 #if defined(CONFIG_FSL_DMA) 451 dma_init(); 452 #endif 453 #ifdef CONFIG_FSL_CORENET 454 corenet_tb_init(); 455 #endif 456 init_used_tlb_cams(); 457 458 /* Invalidate the CPC before DDR gets enabled */ 459 invalidate_cpc(); 460 461 #ifdef CONFIG_SYS_DCSRBAR_PHYS 462 /* set DCSRCR so that DCSR space is 1G */ 463 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 464 in_be32(&gur->dcsrcr); 465 #endif 466 467 #ifdef CONFIG_SYS_DCSRBAR_PHYS 468 #ifdef CONFIG_DEEP_SLEEP 469 /* disable the console if boot from deep sleep */ 470 if (in_be32(&gur->scrtsr[0]) & (1 << 3)) 471 flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; 472 #endif 473 #endif 474 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 475 fsl_erratum_a007212_workaround(); 476 #endif 477 478 return flag; 479 } 480 481 /* Implement a dummy function for those platforms w/o SERDES */ 482 static void __fsl_serdes__init(void) 483 { 484 return ; 485 } 486 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 487 488 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 489 int enable_cluster_l2(void) 490 { 491 int i = 0; 492 u32 cluster, svr = get_svr(); 493 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 494 struct ccsr_cluster_l2 __iomem *l2cache; 495 496 /* only the L2 of first cluster should be enabled as expected on T4080, 497 * but there is no EOC in the first cluster as HW sake, so return here 498 * to skip enabling L2 cache of the 2nd cluster. 499 */ 500 if (SVR_SOC_VER(svr) == SVR_T4080) 501 return 0; 502 503 cluster = in_be32(&gur->tp_cluster[i].lower); 504 if (cluster & TP_CLUSTER_EOC) 505 return 0; 506 507 /* The first cache has already been set up, so skip it */ 508 i++; 509 510 /* Look through the remaining clusters, and set up their caches */ 511 do { 512 int j, cluster_valid = 0; 513 514 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 515 516 cluster = in_be32(&gur->tp_cluster[i].lower); 517 518 /* check that at least one core/accel is enabled in cluster */ 519 for (j = 0; j < 4; j++) { 520 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 521 u32 type = in_be32(&gur->tp_ityp[idx]); 522 523 if ((type & TP_ITYP_AV) && 524 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 525 cluster_valid = 1; 526 } 527 528 if (cluster_valid) { 529 /* set stash ID to (cluster) * 2 + 32 + 1 */ 530 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 531 532 printf("enable l2 for cluster %d %p\n", i, l2cache); 533 534 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 535 while ((in_be32(&l2cache->l2csr0) 536 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 537 ; 538 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 539 } 540 i++; 541 } while (!(cluster & TP_CLUSTER_EOC)); 542 543 return 0; 544 } 545 #endif 546 547 /* 548 * Initialize L2 as cache. 549 * 550 * The newer 8548, etc, parts have twice as much cache, but 551 * use the same bit-encoding as the older 8555, etc, parts. 552 * 553 */ 554 int cpu_init_r(void) 555 { 556 __maybe_unused u32 svr = get_svr(); 557 #ifdef CONFIG_SYS_LBC_LCRR 558 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 559 #endif 560 #ifdef CONFIG_L2_CACHE 561 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 562 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 563 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 564 #endif 565 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 566 extern int spin_table_compat; 567 const char *spin; 568 #endif 569 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 570 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 571 #endif 572 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 573 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 574 /* 575 * CPU22 and NMG_CPU_A011 share the same workaround. 576 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 577 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 578 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 579 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 580 * be disabled by hwconfig with syntax: 581 * 582 * fsl_cpu_a011:disable 583 */ 584 extern int enable_cpu_a011_workaround; 585 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 586 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 587 #else 588 char buffer[HWCONFIG_BUFFER_SIZE]; 589 char *buf = NULL; 590 int n, res; 591 592 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 593 if (n > 0) 594 buf = buffer; 595 596 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 597 if (res > 0) 598 enable_cpu_a011_workaround = 0; 599 else { 600 if (n >= HWCONFIG_BUFFER_SIZE) { 601 printf("fsl_cpu_a011 was not found. hwconfig variable " 602 "may be too long\n"); 603 } 604 enable_cpu_a011_workaround = 605 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 606 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 607 } 608 #endif 609 if (enable_cpu_a011_workaround) { 610 flush_dcache(); 611 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 612 sync(); 613 } 614 #endif 615 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 616 /* 617 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 618 * in write shadow mode. Checking DCWS before setting SPR 976. 619 */ 620 if (mfspr(L1CSR2) & L1CSR2_DCWS) 621 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 622 #endif 623 624 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 625 spin = getenv("spin_table_compat"); 626 if (spin && (*spin == 'n')) 627 spin_table_compat = 0; 628 else 629 spin_table_compat = 1; 630 #endif 631 632 puts ("L2: "); 633 634 #if defined(CONFIG_L2_CACHE) 635 volatile uint cache_ctl; 636 uint ver; 637 u32 l2siz_field; 638 639 ver = SVR_SOC_VER(svr); 640 641 asm("msync;isync"); 642 cache_ctl = l2cache->l2ctl; 643 644 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 645 if (cache_ctl & MPC85xx_L2CTL_L2E) { 646 /* Clear L2 SRAM memory-mapped base address */ 647 out_be32(&l2cache->l2srbar0, 0x0); 648 out_be32(&l2cache->l2srbar1, 0x0); 649 650 /* set MBECCDIS=0, SBECCDIS=0 */ 651 clrbits_be32(&l2cache->l2errdis, 652 (MPC85xx_L2ERRDIS_MBECC | 653 MPC85xx_L2ERRDIS_SBECC)); 654 655 /* set L2E=0, L2SRAM=0 */ 656 clrbits_be32(&l2cache->l2ctl, 657 (MPC85xx_L2CTL_L2E | 658 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 659 } 660 #endif 661 662 l2siz_field = (cache_ctl >> 28) & 0x3; 663 664 switch (l2siz_field) { 665 case 0x0: 666 printf(" unknown size (0x%08x)\n", cache_ctl); 667 return -1; 668 break; 669 case 0x1: 670 if (ver == SVR_8540 || ver == SVR_8560 || 671 ver == SVR_8541 || ver == SVR_8555) { 672 puts("128 KiB "); 673 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 674 cache_ctl = 0xc4000000; 675 } else { 676 puts("256 KiB "); 677 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 678 } 679 break; 680 case 0x2: 681 if (ver == SVR_8540 || ver == SVR_8560 || 682 ver == SVR_8541 || ver == SVR_8555) { 683 puts("256 KiB "); 684 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 685 cache_ctl = 0xc8000000; 686 } else { 687 puts("512 KiB "); 688 /* set L2E=1, L2I=1, & L2SRAM=0 */ 689 cache_ctl = 0xc0000000; 690 } 691 break; 692 case 0x3: 693 puts("1024 KiB "); 694 /* set L2E=1, L2I=1, & L2SRAM=0 */ 695 cache_ctl = 0xc0000000; 696 break; 697 } 698 699 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 700 puts("already enabled"); 701 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 702 u32 l2srbar = l2cache->l2srbar0; 703 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 704 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 705 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 706 l2cache->l2srbar0 = l2srbar; 707 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 708 } 709 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 710 puts("\n"); 711 } else { 712 asm("msync;isync"); 713 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 714 asm("msync;isync"); 715 puts("enabled\n"); 716 } 717 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 718 if (SVR_SOC_VER(svr) == SVR_P2040) { 719 puts("N/A\n"); 720 goto skip_l2; 721 } 722 723 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 724 725 /* invalidate the L2 cache */ 726 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 727 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 728 ; 729 730 #ifdef CONFIG_SYS_CACHE_STASHING 731 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 732 mtspr(SPRN_L2CSR1, (32 + 1)); 733 #endif 734 735 /* enable the cache */ 736 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 737 738 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 739 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 740 ; 741 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 742 } 743 744 skip_l2: 745 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 746 if (l2cache->l2csr0 & L2CSR0_L2E) 747 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 748 " enabled\n"); 749 750 enable_cluster_l2(); 751 #else 752 puts("disabled\n"); 753 #endif 754 755 #if defined(CONFIG_RAMBOOT_PBL) 756 disable_cpc_sram(); 757 #endif 758 enable_cpc(); 759 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 760 enable_tdm_law(); 761 #endif 762 763 #ifndef CONFIG_SYS_FSL_NO_SERDES 764 /* needs to be in ram since code uses global static vars */ 765 fsl_serdes_init(); 766 #endif 767 768 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 769 #define MCFGR_AXIPIPE 0x000000f0 770 if (IS_SVR_REV(svr, 1, 0)) 771 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); 772 #endif 773 774 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 775 if (IS_SVR_REV(svr, 1, 0)) { 776 int i; 777 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 778 779 for (i = 0; i < 12; i++) { 780 p += i + (i > 5 ? 11 : 0); 781 out_be32(p, 0x2); 782 } 783 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 784 out_be32(p, 0x34); 785 } 786 #endif 787 788 #ifdef CONFIG_SYS_SRIO 789 srio_init(); 790 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 791 char *s = getenv("bootmaster"); 792 if (s) { 793 if (!strcmp(s, "SRIO1")) { 794 srio_boot_master(1); 795 srio_boot_master_release_slave(1); 796 } 797 if (!strcmp(s, "SRIO2")) { 798 srio_boot_master(2); 799 srio_boot_master_release_slave(2); 800 } 801 } 802 #endif 803 #endif 804 805 #if defined(CONFIG_MP) 806 setup_mp(); 807 #endif 808 809 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 810 { 811 if (SVR_MAJ(svr) < 3) { 812 void *p; 813 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 814 setbits_be32(p, 1 << (31 - 14)); 815 } 816 } 817 #endif 818 819 #ifdef CONFIG_SYS_LBC_LCRR 820 /* 821 * Modify the CLKDIV field of LCRR register to improve the writing 822 * speed for NOR flash. 823 */ 824 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 825 __raw_readl(&lbc->lcrr); 826 isync(); 827 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 828 udelay(100); 829 #endif 830 #endif 831 832 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 833 { 834 struct ccsr_usb_phy __iomem *usb_phy1 = 835 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 836 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 837 if (has_erratum_a006261()) 838 fsl_erratum_a006261_workaround(usb_phy1); 839 #endif 840 out_be32(&usb_phy1->usb_enable_override, 841 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 842 } 843 #endif 844 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 845 { 846 struct ccsr_usb_phy __iomem *usb_phy2 = 847 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 848 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 849 if (has_erratum_a006261()) 850 fsl_erratum_a006261_workaround(usb_phy2); 851 #endif 852 out_be32(&usb_phy2->usb_enable_override, 853 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 854 } 855 #endif 856 857 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 858 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 859 * multi-bit ECC errors which has impact on performance, so software 860 * should disable all ECC reporting from USB1 and USB2. 861 */ 862 if (IS_SVR_REV(get_svr(), 1, 0)) { 863 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 864 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 865 setbits_be32(&dcfg->ecccr1, 866 (DCSR_DCFG_ECC_DISABLE_USB1 | 867 DCSR_DCFG_ECC_DISABLE_USB2)); 868 } 869 #endif 870 871 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 872 struct ccsr_usb_phy __iomem *usb_phy = 873 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 874 setbits_be32(&usb_phy->pllprg[1], 875 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 876 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 877 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 878 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 879 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 880 usb_single_source_clk_configure(usb_phy); 881 #endif 882 setbits_be32(&usb_phy->port1.ctrl, 883 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 884 setbits_be32(&usb_phy->port1.drvvbuscfg, 885 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 886 setbits_be32(&usb_phy->port1.pwrfltcfg, 887 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 888 setbits_be32(&usb_phy->port2.ctrl, 889 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 890 setbits_be32(&usb_phy->port2.drvvbuscfg, 891 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 892 setbits_be32(&usb_phy->port2.pwrfltcfg, 893 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 894 895 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 896 if (has_erratum_a006261()) 897 fsl_erratum_a006261_workaround(usb_phy); 898 #endif 899 900 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 901 902 #ifdef CONFIG_FMAN_ENET 903 fman_enet_init(); 904 #endif 905 906 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 907 /* 908 * For P1022/1013 Rev1.0 silicon, after power on SATA host 909 * controller is configured in legacy mode instead of the 910 * expected enterprise mode. Software needs to clear bit[28] 911 * of HControl register to change to enterprise mode from 912 * legacy mode. We assume that the controller is offline. 913 */ 914 if (IS_SVR_REV(svr, 1, 0) && 915 ((SVR_SOC_VER(svr) == SVR_P1022) || 916 (SVR_SOC_VER(svr) == SVR_P1013))) { 917 fsl_sata_reg_t *reg; 918 919 /* first SATA controller */ 920 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 921 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 922 923 /* second SATA controller */ 924 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 925 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 926 } 927 #endif 928 929 init_used_tlb_cams(); 930 931 return 0; 932 } 933 934 void arch_preboot_os(void) 935 { 936 u32 msr; 937 938 /* 939 * We are changing interrupt offsets and are about to boot the OS so 940 * we need to make sure we disable all async interrupts. EE is already 941 * disabled by the time we get called. 942 */ 943 msr = mfmsr(); 944 msr &= ~(MSR_ME|MSR_CE); 945 mtmsr(msr); 946 } 947 948 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 949 int sata_initialize(void) 950 { 951 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 952 return __sata_initialize(); 953 954 return 1; 955 } 956 #endif 957 958 void cpu_secondary_init_r(void) 959 { 960 #ifdef CONFIG_U_QE 961 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 962 #elif defined CONFIG_QE 963 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 964 #endif 965 966 #ifdef CONFIG_QE 967 qe_init(qe_base); 968 qe_reset(); 969 #endif 970 } 971