1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <fsl_errata.h> 23 #include <asm/fsl_law.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_srio.h> 26 #include <fsl_usb.h> 27 #include <hwconfig.h> 28 #include <linux/compiler.h> 29 #include "mp.h" 30 #ifdef CONFIG_CHAIN_OF_TRUST 31 #include <fsl_validate.h> 32 #endif 33 #ifdef CONFIG_FSL_CAAM 34 #include <fsl_sec.h> 35 #endif 36 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 37 #include <nand.h> 38 #include <errno.h> 39 #endif 40 41 #include "../../../../drivers/block/fsl_sata.h" 42 #ifdef CONFIG_U_QE 43 #include "../../../../drivers/qe/qe.h" 44 #endif 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 49 /* 50 * For deriving usb clock from 100MHz sysclk, reference divisor is set 51 * to a value of 5, which gives an intermediate value 20(100/5). The 52 * multiplication factor integer is set to 24, which when multiplied to 53 * above intermediate value provides clock for usb ip. 54 */ 55 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) 56 { 57 sys_info_t sysinfo; 58 59 get_sys_info(&sysinfo); 60 if (sysinfo.diff_sysclk == 1) { 61 clrbits_be32(&usb_phy->pllprg[1], 62 CONFIG_SYS_FSL_USB_PLLPRG2_MFI); 63 setbits_be32(&usb_phy->pllprg[1], 64 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | 65 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | 66 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); 67 } 68 } 69 #endif 70 71 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 72 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 73 { 74 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 75 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 76 77 /* Increase Disconnect Threshold by 50mV */ 78 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 79 INC_DCNT_THRESHOLD_50MV; 80 /* Enable programming of USB High speed Disconnect threshold */ 81 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 82 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 83 84 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 85 /* Increase Disconnect Threshold by 50mV */ 86 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 87 INC_DCNT_THRESHOLD_50MV; 88 /* Enable programming of USB High speed Disconnect threshold */ 89 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 90 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 91 #else 92 93 u32 temp = 0; 94 u32 status = in_be32(&usb_phy->status1); 95 96 u32 squelch_prog_rd_0_2 = 97 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 98 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 99 100 u32 squelch_prog_rd_3_5 = 101 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 102 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 103 104 setbits_be32(&usb_phy->config1, 105 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); 106 setbits_be32(&usb_phy->config2, 107 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 108 109 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 110 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 111 112 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 113 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 114 #endif 115 } 116 #endif 117 118 119 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 120 extern qe_iop_conf_t qe_iop_conf_tab[]; 121 extern void qe_config_iopin(u8 port, u8 pin, int dir, 122 int open_drain, int assign); 123 extern void qe_init(uint qe_base); 124 extern void qe_reset(void); 125 126 static void config_qe_ioports(void) 127 { 128 u8 port, pin; 129 int dir, open_drain, assign; 130 int i; 131 132 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 133 port = qe_iop_conf_tab[i].port; 134 pin = qe_iop_conf_tab[i].pin; 135 dir = qe_iop_conf_tab[i].dir; 136 open_drain = qe_iop_conf_tab[i].open_drain; 137 assign = qe_iop_conf_tab[i].assign; 138 qe_config_iopin(port, pin, dir, open_drain, assign); 139 } 140 } 141 #endif 142 143 #ifdef CONFIG_CPM2 144 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 145 { 146 int portnum; 147 148 for (portnum = 0; portnum < 4; portnum++) { 149 uint pmsk = 0, 150 ppar = 0, 151 psor = 0, 152 pdir = 0, 153 podr = 0, 154 pdat = 0; 155 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 156 iop_conf_t *eiopc = iopc + 32; 157 uint msk = 1; 158 159 /* 160 * NOTE: 161 * index 0 refers to pin 31, 162 * index 31 refers to pin 0 163 */ 164 while (iopc < eiopc) { 165 if (iopc->conf) { 166 pmsk |= msk; 167 if (iopc->ppar) 168 ppar |= msk; 169 if (iopc->psor) 170 psor |= msk; 171 if (iopc->pdir) 172 pdir |= msk; 173 if (iopc->podr) 174 podr |= msk; 175 if (iopc->pdat) 176 pdat |= msk; 177 } 178 179 msk <<= 1; 180 iopc++; 181 } 182 183 if (pmsk != 0) { 184 volatile ioport_t *iop = ioport_addr (cpm, portnum); 185 uint tpmsk = ~pmsk; 186 187 /* 188 * the (somewhat confused) paragraph at the 189 * bottom of page 35-5 warns that there might 190 * be "unknown behaviour" when programming 191 * PSORx and PDIRx, if PPARx = 1, so I 192 * decided this meant I had to disable the 193 * dedicated function first, and enable it 194 * last. 195 */ 196 iop->ppar &= tpmsk; 197 iop->psor = (iop->psor & tpmsk) | psor; 198 iop->podr = (iop->podr & tpmsk) | podr; 199 iop->pdat = (iop->pdat & tpmsk) | pdat; 200 iop->pdir = (iop->pdir & tpmsk) | pdir; 201 iop->ppar |= ppar; 202 } 203 } 204 } 205 #endif 206 207 #ifdef CONFIG_SYS_FSL_CPC 208 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 209 void disable_cpc_sram(void) 210 { 211 int i; 212 213 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 214 215 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 216 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 217 /* find and disable LAW of SRAM */ 218 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 219 220 if (law.index == -1) { 221 printf("\nFatal error happened\n"); 222 return; 223 } 224 disable_law(law.index); 225 226 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 227 out_be32(&cpc->cpccsr0, 0); 228 out_be32(&cpc->cpcsrcr0, 0); 229 } 230 } 231 } 232 #endif 233 234 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 235 #ifdef CONFIG_POST 236 #error POST memory test cannot be enabled with TDM 237 #endif 238 static void enable_tdm_law(void) 239 { 240 int ret; 241 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 242 int tdm_hwconfig_enabled = 0; 243 244 /* 245 * Extract hwconfig from environment since environment 246 * is not setup properly yet. Search for tdm entry in 247 * hwconfig. 248 */ 249 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 250 if (ret > 0) { 251 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 252 /* If tdm is defined in hwconfig, set law for tdm workaround */ 253 if (tdm_hwconfig_enabled) 254 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, 255 LAW_TRGT_IF_CCSR); 256 } 257 } 258 #endif 259 260 void enable_cpc(void) 261 { 262 int i; 263 int ret; 264 u32 size = 0; 265 u32 cpccfg0; 266 char buffer[HWCONFIG_BUFFER_SIZE]; 267 char cpc_subarg[16]; 268 bool have_hwconfig = false; 269 int cpc_args = 0; 270 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 271 272 /* Extract hwconfig from environment */ 273 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 274 if (ret > 0) { 275 /* 276 * If "en_cpc" is not defined in hwconfig then by default all 277 * cpcs are enable. If this config is defined then individual 278 * cpcs which have to be enabled should also be defined. 279 * e.g en_cpc:cpc1,cpc2; 280 */ 281 if (hwconfig_f("en_cpc", buffer)) 282 have_hwconfig = true; 283 } 284 285 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 286 if (have_hwconfig) { 287 sprintf(cpc_subarg, "cpc%u", i + 1); 288 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); 289 if (cpc_args == 0) 290 continue; 291 } 292 cpccfg0 = in_be32(&cpc->cpccfg0); 293 size += CPC_CFG0_SZ_K(cpccfg0); 294 295 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 296 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 297 #endif 298 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 299 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 300 #endif 301 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 302 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 303 #endif 304 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 305 if (has_erratum_a006379()) { 306 setbits_be32(&cpc->cpchdbcr0, 307 CPC_HDBCR0_SPLRU_LEVEL_EN); 308 } 309 #endif 310 311 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 312 /* Read back to sync write */ 313 in_be32(&cpc->cpccsr0); 314 315 } 316 317 puts("Corenet Platform Cache: "); 318 print_size(size * 1024, " enabled\n"); 319 } 320 321 static void invalidate_cpc(void) 322 { 323 int i; 324 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 325 326 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 327 /* skip CPC when it used as all SRAM */ 328 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 329 continue; 330 /* Flash invalidate the CPC and clear all the locks */ 331 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 332 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 333 ; 334 } 335 } 336 #else 337 #define enable_cpc() 338 #define invalidate_cpc() 339 #define disable_cpc_sram() 340 #endif /* CONFIG_SYS_FSL_CPC */ 341 342 /* 343 * Breathe some life into the CPU... 344 * 345 * Set up the memory map 346 * initialize a bunch of registers 347 */ 348 349 #ifdef CONFIG_FSL_CORENET 350 static void corenet_tb_init(void) 351 { 352 volatile ccsr_rcpm_t *rcpm = 353 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 354 volatile ccsr_pic_t *pic = 355 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 356 u32 whoami = in_be32(&pic->whoami); 357 358 /* Enable the timebase register for this core */ 359 out_be32(&rcpm->ctbenrl, (1 << whoami)); 360 } 361 #endif 362 363 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 364 void fsl_erratum_a007212_workaround(void) 365 { 366 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 367 u32 ddr_pll_ratio; 368 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); 369 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); 370 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); 371 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 372 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); 373 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); 374 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 375 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); 376 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); 377 #endif 378 #endif 379 /* 380 * Even this workaround applies to selected version of SoCs, it is 381 * safe to apply to all versions, with the limitation of odd ratios. 382 * If RCW has disabled DDR PLL, we have to apply this workaround, 383 * otherwise DDR will not work. 384 */ 385 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 386 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & 387 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 388 /* check if RCW sets ratio to 0, required by this workaround */ 389 if (ddr_pll_ratio != 0) 390 return; 391 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 392 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 393 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 394 /* check if reserved bits have the desired ratio */ 395 if (ddr_pll_ratio == 0) { 396 printf("Error: Unknown DDR PLL ratio!\n"); 397 return; 398 } 399 ddr_pll_ratio >>= 1; 400 401 setbits_be32(plldadcr1, 0x02000001); 402 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 403 setbits_be32(plldadcr2, 0x02000001); 404 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 405 setbits_be32(plldadcr3, 0x02000001); 406 #endif 407 #endif 408 setbits_be32(dpdovrcr4, 0xe0000000); 409 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); 410 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 411 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); 412 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 413 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); 414 #endif 415 #endif 416 udelay(100); 417 clrbits_be32(plldadcr1, 0x02000001); 418 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 419 clrbits_be32(plldadcr2, 0x02000001); 420 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 421 clrbits_be32(plldadcr3, 0x02000001); 422 #endif 423 #endif 424 clrbits_be32(dpdovrcr4, 0xe0000000); 425 } 426 #endif 427 428 ulong cpu_init_f(void) 429 { 430 extern void m8560_cpm_reset (void); 431 #if defined(CONFIG_SYS_DCSRBAR_PHYS) || \ 432 (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)) 433 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 434 #endif 435 #if defined(CONFIG_SECURE_BOOT) 436 struct law_entry law; 437 #endif 438 #ifdef CONFIG_MPC8548 439 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 440 uint svr = get_svr(); 441 442 /* 443 * CPU2 errata workaround: A core hang possible while executing 444 * a msync instruction and a snoopable transaction from an I/O 445 * master tagged to make quick forward progress is present. 446 * Fixed in silicon rev 2.1. 447 */ 448 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 449 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 450 #endif 451 452 disable_tlb(14); 453 disable_tlb(15); 454 455 #if defined(CONFIG_SECURE_BOOT) 456 /* Disable the LAW created for NOR flash by the PBI commands */ 457 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 458 if (law.index != -1) 459 disable_law(law.index); 460 461 #if defined(CONFIG_SYS_CPC_REINIT_F) 462 disable_cpc_sram(); 463 #endif 464 465 #if defined(CONFIG_FSL_CORENET) 466 /* Put PAMU in bypass mode */ 467 out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS); 468 #endif 469 470 #endif 471 472 #ifdef CONFIG_CPM2 473 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 474 #endif 475 476 init_early_memctl_regs(); 477 478 #if defined(CONFIG_CPM2) 479 m8560_cpm_reset(); 480 #endif 481 482 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 483 /* Config QE ioports */ 484 config_qe_ioports(); 485 #endif 486 487 #if defined(CONFIG_FSL_DMA) 488 dma_init(); 489 #endif 490 #ifdef CONFIG_FSL_CORENET 491 corenet_tb_init(); 492 #endif 493 init_used_tlb_cams(); 494 495 /* Invalidate the CPC before DDR gets enabled */ 496 invalidate_cpc(); 497 498 #ifdef CONFIG_SYS_DCSRBAR_PHYS 499 /* set DCSRCR so that DCSR space is 1G */ 500 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 501 in_be32(&gur->dcsrcr); 502 #endif 503 504 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 505 fsl_erratum_a007212_workaround(); 506 #endif 507 508 return 0; 509 } 510 511 /* Implement a dummy function for those platforms w/o SERDES */ 512 static void __fsl_serdes__init(void) 513 { 514 return ; 515 } 516 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 517 518 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 519 int enable_cluster_l2(void) 520 { 521 int i = 0; 522 u32 cluster, svr = get_svr(); 523 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 524 struct ccsr_cluster_l2 __iomem *l2cache; 525 526 /* only the L2 of first cluster should be enabled as expected on T4080, 527 * but there is no EOC in the first cluster as HW sake, so return here 528 * to skip enabling L2 cache of the 2nd cluster. 529 */ 530 if (SVR_SOC_VER(svr) == SVR_T4080) 531 return 0; 532 533 cluster = in_be32(&gur->tp_cluster[i].lower); 534 if (cluster & TP_CLUSTER_EOC) 535 return 0; 536 537 /* The first cache has already been set up, so skip it */ 538 i++; 539 540 /* Look through the remaining clusters, and set up their caches */ 541 do { 542 int j, cluster_valid = 0; 543 544 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 545 546 cluster = in_be32(&gur->tp_cluster[i].lower); 547 548 /* check that at least one core/accel is enabled in cluster */ 549 for (j = 0; j < 4; j++) { 550 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 551 u32 type = in_be32(&gur->tp_ityp[idx]); 552 553 if ((type & TP_ITYP_AV) && 554 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 555 cluster_valid = 1; 556 } 557 558 if (cluster_valid) { 559 /* set stash ID to (cluster) * 2 + 32 + 1 */ 560 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 561 562 printf("enable l2 for cluster %d %p\n", i, l2cache); 563 564 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 565 while ((in_be32(&l2cache->l2csr0) 566 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 567 ; 568 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 569 } 570 i++; 571 } while (!(cluster & TP_CLUSTER_EOC)); 572 573 return 0; 574 } 575 #endif 576 577 /* 578 * Initialize L2 as cache. 579 */ 580 int l2cache_init(void) 581 { 582 __maybe_unused u32 svr = get_svr(); 583 #ifdef CONFIG_L2_CACHE 584 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 585 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 586 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 587 #endif 588 589 puts ("L2: "); 590 591 #if defined(CONFIG_L2_CACHE) 592 volatile uint cache_ctl; 593 uint ver; 594 u32 l2siz_field; 595 596 ver = SVR_SOC_VER(svr); 597 598 asm("msync;isync"); 599 cache_ctl = l2cache->l2ctl; 600 601 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 602 if (cache_ctl & MPC85xx_L2CTL_L2E) { 603 /* Clear L2 SRAM memory-mapped base address */ 604 out_be32(&l2cache->l2srbar0, 0x0); 605 out_be32(&l2cache->l2srbar1, 0x0); 606 607 /* set MBECCDIS=0, SBECCDIS=0 */ 608 clrbits_be32(&l2cache->l2errdis, 609 (MPC85xx_L2ERRDIS_MBECC | 610 MPC85xx_L2ERRDIS_SBECC)); 611 612 /* set L2E=0, L2SRAM=0 */ 613 clrbits_be32(&l2cache->l2ctl, 614 (MPC85xx_L2CTL_L2E | 615 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 616 } 617 #endif 618 619 l2siz_field = (cache_ctl >> 28) & 0x3; 620 621 switch (l2siz_field) { 622 case 0x0: 623 printf(" unknown size (0x%08x)\n", cache_ctl); 624 return -1; 625 break; 626 case 0x1: 627 if (ver == SVR_8540 || ver == SVR_8560 || 628 ver == SVR_8541 || ver == SVR_8555) { 629 puts("128 KiB "); 630 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 631 cache_ctl = 0xc4000000; 632 } else { 633 puts("256 KiB "); 634 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 635 } 636 break; 637 case 0x2: 638 if (ver == SVR_8540 || ver == SVR_8560 || 639 ver == SVR_8541 || ver == SVR_8555) { 640 puts("256 KiB "); 641 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 642 cache_ctl = 0xc8000000; 643 } else { 644 puts("512 KiB "); 645 /* set L2E=1, L2I=1, & L2SRAM=0 */ 646 cache_ctl = 0xc0000000; 647 } 648 break; 649 case 0x3: 650 puts("1024 KiB "); 651 /* set L2E=1, L2I=1, & L2SRAM=0 */ 652 cache_ctl = 0xc0000000; 653 break; 654 } 655 656 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 657 puts("already enabled"); 658 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 659 u32 l2srbar = l2cache->l2srbar0; 660 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 661 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 662 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 663 l2cache->l2srbar0 = l2srbar; 664 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 665 } 666 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 667 puts("\n"); 668 } else { 669 asm("msync;isync"); 670 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 671 asm("msync;isync"); 672 puts("enabled\n"); 673 } 674 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 675 if (SVR_SOC_VER(svr) == SVR_P2040) { 676 puts("N/A\n"); 677 goto skip_l2; 678 } 679 680 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 681 682 /* invalidate the L2 cache */ 683 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 684 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 685 ; 686 687 #ifdef CONFIG_SYS_CACHE_STASHING 688 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 689 mtspr(SPRN_L2CSR1, (32 + 1)); 690 #endif 691 692 /* enable the cache */ 693 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 694 695 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 696 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 697 ; 698 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 699 } 700 701 skip_l2: 702 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 703 if (l2cache->l2csr0 & L2CSR0_L2E) 704 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 705 " enabled\n"); 706 707 enable_cluster_l2(); 708 #else 709 puts("disabled\n"); 710 #endif 711 712 return 0; 713 } 714 715 /* 716 * 717 * The newer 8548, etc, parts have twice as much cache, but 718 * use the same bit-encoding as the older 8555, etc, parts. 719 * 720 */ 721 int cpu_init_r(void) 722 { 723 __maybe_unused u32 svr = get_svr(); 724 #ifdef CONFIG_SYS_LBC_LCRR 725 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 726 #endif 727 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 728 extern int spin_table_compat; 729 const char *spin; 730 #endif 731 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 732 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 733 #endif 734 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 735 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 736 /* 737 * CPU22 and NMG_CPU_A011 share the same workaround. 738 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 739 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 740 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 741 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 742 * be disabled by hwconfig with syntax: 743 * 744 * fsl_cpu_a011:disable 745 */ 746 extern int enable_cpu_a011_workaround; 747 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 748 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 749 #else 750 char buffer[HWCONFIG_BUFFER_SIZE]; 751 char *buf = NULL; 752 int n, res; 753 754 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 755 if (n > 0) 756 buf = buffer; 757 758 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 759 if (res > 0) { 760 enable_cpu_a011_workaround = 0; 761 } else { 762 if (n >= HWCONFIG_BUFFER_SIZE) { 763 printf("fsl_cpu_a011 was not found. hwconfig variable " 764 "may be too long\n"); 765 } 766 enable_cpu_a011_workaround = 767 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 768 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 769 } 770 #endif 771 if (enable_cpu_a011_workaround) { 772 flush_dcache(); 773 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 774 sync(); 775 } 776 #endif 777 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 778 /* 779 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 780 * in write shadow mode. Checking DCWS before setting SPR 976. 781 */ 782 if (mfspr(L1CSR2) & L1CSR2_DCWS) 783 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 784 #endif 785 786 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 787 spin = getenv("spin_table_compat"); 788 if (spin && (*spin == 'n')) 789 spin_table_compat = 0; 790 else 791 spin_table_compat = 1; 792 #endif 793 794 l2cache_init(); 795 #if defined(CONFIG_RAMBOOT_PBL) 796 disable_cpc_sram(); 797 #endif 798 enable_cpc(); 799 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 800 enable_tdm_law(); 801 #endif 802 803 #ifndef CONFIG_SYS_FSL_NO_SERDES 804 /* needs to be in ram since code uses global static vars */ 805 fsl_serdes_init(); 806 #endif 807 808 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 809 #define MCFGR_AXIPIPE 0x000000f0 810 if (IS_SVR_REV(svr, 1, 0)) 811 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE); 812 #endif 813 814 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 815 if (IS_SVR_REV(svr, 1, 0)) { 816 int i; 817 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 818 819 for (i = 0; i < 12; i++) { 820 p += i + (i > 5 ? 11 : 0); 821 out_be32(p, 0x2); 822 } 823 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 824 out_be32(p, 0x34); 825 } 826 #endif 827 828 #ifdef CONFIG_SYS_SRIO 829 srio_init(); 830 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 831 char *s = getenv("bootmaster"); 832 if (s) { 833 if (!strcmp(s, "SRIO1")) { 834 srio_boot_master(1); 835 srio_boot_master_release_slave(1); 836 } 837 if (!strcmp(s, "SRIO2")) { 838 srio_boot_master(2); 839 srio_boot_master_release_slave(2); 840 } 841 } 842 #endif 843 #endif 844 845 #if defined(CONFIG_MP) 846 setup_mp(); 847 #endif 848 849 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 850 { 851 if (SVR_MAJ(svr) < 3) { 852 void *p; 853 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 854 setbits_be32(p, 1 << (31 - 14)); 855 } 856 } 857 #endif 858 859 #ifdef CONFIG_SYS_LBC_LCRR 860 /* 861 * Modify the CLKDIV field of LCRR register to improve the writing 862 * speed for NOR flash. 863 */ 864 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 865 __raw_readl(&lbc->lcrr); 866 isync(); 867 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 868 udelay(100); 869 #endif 870 #endif 871 872 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 873 { 874 struct ccsr_usb_phy __iomem *usb_phy1 = 875 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 876 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 877 if (has_erratum_a006261()) 878 fsl_erratum_a006261_workaround(usb_phy1); 879 #endif 880 out_be32(&usb_phy1->usb_enable_override, 881 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 882 } 883 #endif 884 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 885 { 886 struct ccsr_usb_phy __iomem *usb_phy2 = 887 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 888 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 889 if (has_erratum_a006261()) 890 fsl_erratum_a006261_workaround(usb_phy2); 891 #endif 892 out_be32(&usb_phy2->usb_enable_override, 893 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 894 } 895 #endif 896 897 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 898 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 899 * multi-bit ECC errors which has impact on performance, so software 900 * should disable all ECC reporting from USB1 and USB2. 901 */ 902 if (IS_SVR_REV(get_svr(), 1, 0)) { 903 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 904 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 905 setbits_be32(&dcfg->ecccr1, 906 (DCSR_DCFG_ECC_DISABLE_USB1 | 907 DCSR_DCFG_ECC_DISABLE_USB2)); 908 } 909 #endif 910 911 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 912 struct ccsr_usb_phy __iomem *usb_phy = 913 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 914 setbits_be32(&usb_phy->pllprg[1], 915 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 916 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 917 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 918 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 919 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 920 usb_single_source_clk_configure(usb_phy); 921 #endif 922 setbits_be32(&usb_phy->port1.ctrl, 923 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 924 setbits_be32(&usb_phy->port1.drvvbuscfg, 925 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 926 setbits_be32(&usb_phy->port1.pwrfltcfg, 927 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 928 setbits_be32(&usb_phy->port2.ctrl, 929 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 930 setbits_be32(&usb_phy->port2.drvvbuscfg, 931 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 932 setbits_be32(&usb_phy->port2.pwrfltcfg, 933 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 934 935 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 936 if (has_erratum_a006261()) 937 fsl_erratum_a006261_workaround(usb_phy); 938 #endif 939 940 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 941 942 #ifdef CONFIG_FMAN_ENET 943 fman_enet_init(); 944 #endif 945 946 #ifdef CONFIG_FSL_CAAM 947 sec_init(); 948 #endif 949 950 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 951 /* 952 * For P1022/1013 Rev1.0 silicon, after power on SATA host 953 * controller is configured in legacy mode instead of the 954 * expected enterprise mode. Software needs to clear bit[28] 955 * of HControl register to change to enterprise mode from 956 * legacy mode. We assume that the controller is offline. 957 */ 958 if (IS_SVR_REV(svr, 1, 0) && 959 ((SVR_SOC_VER(svr) == SVR_P1022) || 960 (SVR_SOC_VER(svr) == SVR_P1013))) { 961 fsl_sata_reg_t *reg; 962 963 /* first SATA controller */ 964 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 965 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 966 967 /* second SATA controller */ 968 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 969 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 970 } 971 #endif 972 973 init_used_tlb_cams(); 974 975 return 0; 976 } 977 978 void arch_preboot_os(void) 979 { 980 u32 msr; 981 982 /* 983 * We are changing interrupt offsets and are about to boot the OS so 984 * we need to make sure we disable all async interrupts. EE is already 985 * disabled by the time we get called. 986 */ 987 msr = mfmsr(); 988 msr &= ~(MSR_ME|MSR_CE); 989 mtmsr(msr); 990 } 991 992 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 993 int sata_initialize(void) 994 { 995 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 996 return __sata_initialize(); 997 998 return 1; 999 } 1000 #endif 1001 1002 void cpu_secondary_init_r(void) 1003 { 1004 #ifdef CONFIG_U_QE 1005 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 1006 #elif defined CONFIG_QE 1007 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 1008 #endif 1009 1010 #ifdef CONFIG_QE 1011 qe_init(qe_base); 1012 qe_reset(); 1013 #endif 1014 } 1015 1016 #ifdef CONFIG_BOARD_LATE_INIT 1017 int board_late_init(void) 1018 { 1019 #ifdef CONFIG_CHAIN_OF_TRUST 1020 fsl_setenv_chain_of_trust(); 1021 #endif 1022 1023 return 0; 1024 } 1025 #endif 1026