1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <asm/fsl_errata.h> 23 #include <asm/fsl_law.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_srio.h> 26 #include <fsl_usb.h> 27 #include <hwconfig.h> 28 #include <linux/compiler.h> 29 #include "mp.h" 30 #ifdef CONFIG_FSL_CAAM 31 #include <fsl_sec.h> 32 #endif 33 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 34 #include <nand.h> 35 #include <errno.h> 36 #endif 37 38 #include "../../../../drivers/block/fsl_sata.h" 39 #ifdef CONFIG_U_QE 40 #include "../../../../drivers/qe/qe.h" 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 46 /* 47 * For deriving usb clock from 100MHz sysclk, reference divisor is set 48 * to a value of 5, which gives an intermediate value 20(100/5). The 49 * multiplication factor integer is set to 24, which when multiplied to 50 * above intermediate value provides clock for usb ip. 51 */ 52 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) 53 { 54 sys_info_t sysinfo; 55 56 get_sys_info(&sysinfo); 57 if (sysinfo.diff_sysclk == 1) { 58 clrbits_be32(&usb_phy->pllprg[1], 59 CONFIG_SYS_FSL_USB_PLLPRG2_MFI); 60 setbits_be32(&usb_phy->pllprg[1], 61 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | 62 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | 63 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); 64 } 65 } 66 #endif 67 68 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 69 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 70 { 71 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 72 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 73 74 /* Increase Disconnect Threshold by 50mV */ 75 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 76 INC_DCNT_THRESHOLD_50MV; 77 /* Enable programming of USB High speed Disconnect threshold */ 78 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 79 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 80 81 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 82 /* Increase Disconnect Threshold by 50mV */ 83 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 84 INC_DCNT_THRESHOLD_50MV; 85 /* Enable programming of USB High speed Disconnect threshold */ 86 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 87 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 88 #else 89 90 u32 temp = 0; 91 u32 status = in_be32(&usb_phy->status1); 92 93 u32 squelch_prog_rd_0_2 = 94 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 95 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 96 97 u32 squelch_prog_rd_3_5 = 98 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 99 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 100 101 setbits_be32(&usb_phy->config1, 102 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); 103 setbits_be32(&usb_phy->config2, 104 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 105 106 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 107 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 108 109 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 110 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 111 #endif 112 } 113 #endif 114 115 116 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 117 extern qe_iop_conf_t qe_iop_conf_tab[]; 118 extern void qe_config_iopin(u8 port, u8 pin, int dir, 119 int open_drain, int assign); 120 extern void qe_init(uint qe_base); 121 extern void qe_reset(void); 122 123 static void config_qe_ioports(void) 124 { 125 u8 port, pin; 126 int dir, open_drain, assign; 127 int i; 128 129 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 130 port = qe_iop_conf_tab[i].port; 131 pin = qe_iop_conf_tab[i].pin; 132 dir = qe_iop_conf_tab[i].dir; 133 open_drain = qe_iop_conf_tab[i].open_drain; 134 assign = qe_iop_conf_tab[i].assign; 135 qe_config_iopin(port, pin, dir, open_drain, assign); 136 } 137 } 138 #endif 139 140 #ifdef CONFIG_CPM2 141 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 142 { 143 int portnum; 144 145 for (portnum = 0; portnum < 4; portnum++) { 146 uint pmsk = 0, 147 ppar = 0, 148 psor = 0, 149 pdir = 0, 150 podr = 0, 151 pdat = 0; 152 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 153 iop_conf_t *eiopc = iopc + 32; 154 uint msk = 1; 155 156 /* 157 * NOTE: 158 * index 0 refers to pin 31, 159 * index 31 refers to pin 0 160 */ 161 while (iopc < eiopc) { 162 if (iopc->conf) { 163 pmsk |= msk; 164 if (iopc->ppar) 165 ppar |= msk; 166 if (iopc->psor) 167 psor |= msk; 168 if (iopc->pdir) 169 pdir |= msk; 170 if (iopc->podr) 171 podr |= msk; 172 if (iopc->pdat) 173 pdat |= msk; 174 } 175 176 msk <<= 1; 177 iopc++; 178 } 179 180 if (pmsk != 0) { 181 volatile ioport_t *iop = ioport_addr (cpm, portnum); 182 uint tpmsk = ~pmsk; 183 184 /* 185 * the (somewhat confused) paragraph at the 186 * bottom of page 35-5 warns that there might 187 * be "unknown behaviour" when programming 188 * PSORx and PDIRx, if PPARx = 1, so I 189 * decided this meant I had to disable the 190 * dedicated function first, and enable it 191 * last. 192 */ 193 iop->ppar &= tpmsk; 194 iop->psor = (iop->psor & tpmsk) | psor; 195 iop->podr = (iop->podr & tpmsk) | podr; 196 iop->pdat = (iop->pdat & tpmsk) | pdat; 197 iop->pdir = (iop->pdir & tpmsk) | pdir; 198 iop->ppar |= ppar; 199 } 200 } 201 } 202 #endif 203 204 #ifdef CONFIG_SYS_FSL_CPC 205 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 206 void disable_cpc_sram(void) 207 { 208 int i; 209 210 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 211 212 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 213 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 214 /* find and disable LAW of SRAM */ 215 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 216 217 if (law.index == -1) { 218 printf("\nFatal error happened\n"); 219 return; 220 } 221 disable_law(law.index); 222 223 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 224 out_be32(&cpc->cpccsr0, 0); 225 out_be32(&cpc->cpcsrcr0, 0); 226 } 227 } 228 } 229 #endif 230 231 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 232 #ifdef CONFIG_POST 233 #error POST memory test cannot be enabled with TDM 234 #endif 235 static void enable_tdm_law(void) 236 { 237 int ret; 238 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 239 int tdm_hwconfig_enabled = 0; 240 241 /* 242 * Extract hwconfig from environment since environment 243 * is not setup properly yet. Search for tdm entry in 244 * hwconfig. 245 */ 246 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 247 if (ret > 0) { 248 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 249 /* If tdm is defined in hwconfig, set law for tdm workaround */ 250 if (tdm_hwconfig_enabled) 251 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, 252 LAW_TRGT_IF_CCSR); 253 } 254 } 255 #endif 256 257 void enable_cpc(void) 258 { 259 int i; 260 int ret; 261 u32 size = 0; 262 u32 cpccfg0; 263 char buffer[HWCONFIG_BUFFER_SIZE]; 264 char cpc_subarg[16]; 265 bool have_hwconfig = false; 266 int cpc_args = 0; 267 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 268 269 /* Extract hwconfig from environment */ 270 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 271 if (ret > 0) { 272 /* 273 * If "en_cpc" is not defined in hwconfig then by default all 274 * cpcs are enable. If this config is defined then individual 275 * cpcs which have to be enabled should also be defined. 276 * e.g en_cpc:cpc1,cpc2; 277 */ 278 if (hwconfig_f("en_cpc", buffer)) 279 have_hwconfig = true; 280 } 281 282 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 283 if (have_hwconfig) { 284 sprintf(cpc_subarg, "cpc%u", i + 1); 285 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); 286 if (cpc_args == 0) 287 continue; 288 } 289 cpccfg0 = in_be32(&cpc->cpccfg0); 290 size += CPC_CFG0_SZ_K(cpccfg0); 291 292 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 293 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 294 #endif 295 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 296 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 297 #endif 298 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 299 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 300 #endif 301 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 302 if (has_erratum_a006379()) { 303 setbits_be32(&cpc->cpchdbcr0, 304 CPC_HDBCR0_SPLRU_LEVEL_EN); 305 } 306 #endif 307 308 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 309 /* Read back to sync write */ 310 in_be32(&cpc->cpccsr0); 311 312 } 313 314 puts("Corenet Platform Cache: "); 315 print_size(size * 1024, " enabled\n"); 316 } 317 318 static void invalidate_cpc(void) 319 { 320 int i; 321 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 322 323 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 324 /* skip CPC when it used as all SRAM */ 325 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 326 continue; 327 /* Flash invalidate the CPC and clear all the locks */ 328 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 329 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 330 ; 331 } 332 } 333 #else 334 #define enable_cpc() 335 #define invalidate_cpc() 336 #define disable_cpc_sram() 337 #endif /* CONFIG_SYS_FSL_CPC */ 338 339 /* 340 * Breathe some life into the CPU... 341 * 342 * Set up the memory map 343 * initialize a bunch of registers 344 */ 345 346 #ifdef CONFIG_FSL_CORENET 347 static void corenet_tb_init(void) 348 { 349 volatile ccsr_rcpm_t *rcpm = 350 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 351 volatile ccsr_pic_t *pic = 352 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 353 u32 whoami = in_be32(&pic->whoami); 354 355 /* Enable the timebase register for this core */ 356 out_be32(&rcpm->ctbenrl, (1 << whoami)); 357 } 358 #endif 359 360 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 361 void fsl_erratum_a007212_workaround(void) 362 { 363 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 364 u32 ddr_pll_ratio; 365 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); 366 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); 367 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); 368 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 369 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); 370 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); 371 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 372 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); 373 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); 374 #endif 375 #endif 376 /* 377 * Even this workaround applies to selected version of SoCs, it is 378 * safe to apply to all versions, with the limitation of odd ratios. 379 * If RCW has disabled DDR PLL, we have to apply this workaround, 380 * otherwise DDR will not work. 381 */ 382 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 383 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & 384 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 385 /* check if RCW sets ratio to 0, required by this workaround */ 386 if (ddr_pll_ratio != 0) 387 return; 388 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 389 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 390 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 391 /* check if reserved bits have the desired ratio */ 392 if (ddr_pll_ratio == 0) { 393 printf("Error: Unknown DDR PLL ratio!\n"); 394 return; 395 } 396 ddr_pll_ratio >>= 1; 397 398 setbits_be32(plldadcr1, 0x02000001); 399 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 400 setbits_be32(plldadcr2, 0x02000001); 401 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 402 setbits_be32(plldadcr3, 0x02000001); 403 #endif 404 #endif 405 setbits_be32(dpdovrcr4, 0xe0000000); 406 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); 407 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 408 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); 409 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 410 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); 411 #endif 412 #endif 413 udelay(100); 414 clrbits_be32(plldadcr1, 0x02000001); 415 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 416 clrbits_be32(plldadcr2, 0x02000001); 417 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 418 clrbits_be32(plldadcr3, 0x02000001); 419 #endif 420 #endif 421 clrbits_be32(dpdovrcr4, 0xe0000000); 422 } 423 #endif 424 425 ulong cpu_init_f(void) 426 { 427 ulong flag = 0; 428 extern void m8560_cpm_reset (void); 429 #ifdef CONFIG_SYS_DCSRBAR_PHYS 430 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 431 #endif 432 #if defined(CONFIG_SECURE_BOOT) 433 struct law_entry law; 434 #endif 435 #ifdef CONFIG_MPC8548 436 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 437 uint svr = get_svr(); 438 439 /* 440 * CPU2 errata workaround: A core hang possible while executing 441 * a msync instruction and a snoopable transaction from an I/O 442 * master tagged to make quick forward progress is present. 443 * Fixed in silicon rev 2.1. 444 */ 445 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 446 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 447 #endif 448 449 disable_tlb(14); 450 disable_tlb(15); 451 452 #if defined(CONFIG_SECURE_BOOT) 453 /* Disable the LAW created for NOR flash by the PBI commands */ 454 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 455 if (law.index != -1) 456 disable_law(law.index); 457 458 #if defined(CONFIG_SYS_CPC_REINIT_F) 459 disable_cpc_sram(); 460 #endif 461 #endif 462 463 #ifdef CONFIG_CPM2 464 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 465 #endif 466 467 init_early_memctl_regs(); 468 469 #if defined(CONFIG_CPM2) 470 m8560_cpm_reset(); 471 #endif 472 473 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 474 /* Config QE ioports */ 475 config_qe_ioports(); 476 #endif 477 478 #if defined(CONFIG_FSL_DMA) 479 dma_init(); 480 #endif 481 #ifdef CONFIG_FSL_CORENET 482 corenet_tb_init(); 483 #endif 484 init_used_tlb_cams(); 485 486 /* Invalidate the CPC before DDR gets enabled */ 487 invalidate_cpc(); 488 489 #ifdef CONFIG_SYS_DCSRBAR_PHYS 490 /* set DCSRCR so that DCSR space is 1G */ 491 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 492 in_be32(&gur->dcsrcr); 493 #endif 494 495 #ifdef CONFIG_SYS_DCSRBAR_PHYS 496 #ifdef CONFIG_DEEP_SLEEP 497 /* disable the console if boot from deep sleep */ 498 if (in_be32(&gur->scrtsr[0]) & (1 << 3)) 499 flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; 500 #endif 501 #endif 502 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 503 fsl_erratum_a007212_workaround(); 504 #endif 505 506 return flag; 507 } 508 509 /* Implement a dummy function for those platforms w/o SERDES */ 510 static void __fsl_serdes__init(void) 511 { 512 return ; 513 } 514 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 515 516 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 517 int enable_cluster_l2(void) 518 { 519 int i = 0; 520 u32 cluster, svr = get_svr(); 521 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 522 struct ccsr_cluster_l2 __iomem *l2cache; 523 524 /* only the L2 of first cluster should be enabled as expected on T4080, 525 * but there is no EOC in the first cluster as HW sake, so return here 526 * to skip enabling L2 cache of the 2nd cluster. 527 */ 528 if (SVR_SOC_VER(svr) == SVR_T4080) 529 return 0; 530 531 cluster = in_be32(&gur->tp_cluster[i].lower); 532 if (cluster & TP_CLUSTER_EOC) 533 return 0; 534 535 /* The first cache has already been set up, so skip it */ 536 i++; 537 538 /* Look through the remaining clusters, and set up their caches */ 539 do { 540 int j, cluster_valid = 0; 541 542 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 543 544 cluster = in_be32(&gur->tp_cluster[i].lower); 545 546 /* check that at least one core/accel is enabled in cluster */ 547 for (j = 0; j < 4; j++) { 548 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 549 u32 type = in_be32(&gur->tp_ityp[idx]); 550 551 if ((type & TP_ITYP_AV) && 552 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 553 cluster_valid = 1; 554 } 555 556 if (cluster_valid) { 557 /* set stash ID to (cluster) * 2 + 32 + 1 */ 558 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 559 560 printf("enable l2 for cluster %d %p\n", i, l2cache); 561 562 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 563 while ((in_be32(&l2cache->l2csr0) 564 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 565 ; 566 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 567 } 568 i++; 569 } while (!(cluster & TP_CLUSTER_EOC)); 570 571 return 0; 572 } 573 #endif 574 575 /* 576 * Initialize L2 as cache. 577 */ 578 int l2cache_init(void) 579 { 580 __maybe_unused u32 svr = get_svr(); 581 #ifdef CONFIG_L2_CACHE 582 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 583 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 584 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 585 #endif 586 587 puts ("L2: "); 588 589 #if defined(CONFIG_L2_CACHE) 590 volatile uint cache_ctl; 591 uint ver; 592 u32 l2siz_field; 593 594 ver = SVR_SOC_VER(svr); 595 596 asm("msync;isync"); 597 cache_ctl = l2cache->l2ctl; 598 599 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 600 if (cache_ctl & MPC85xx_L2CTL_L2E) { 601 /* Clear L2 SRAM memory-mapped base address */ 602 out_be32(&l2cache->l2srbar0, 0x0); 603 out_be32(&l2cache->l2srbar1, 0x0); 604 605 /* set MBECCDIS=0, SBECCDIS=0 */ 606 clrbits_be32(&l2cache->l2errdis, 607 (MPC85xx_L2ERRDIS_MBECC | 608 MPC85xx_L2ERRDIS_SBECC)); 609 610 /* set L2E=0, L2SRAM=0 */ 611 clrbits_be32(&l2cache->l2ctl, 612 (MPC85xx_L2CTL_L2E | 613 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 614 } 615 #endif 616 617 l2siz_field = (cache_ctl >> 28) & 0x3; 618 619 switch (l2siz_field) { 620 case 0x0: 621 printf(" unknown size (0x%08x)\n", cache_ctl); 622 return -1; 623 break; 624 case 0x1: 625 if (ver == SVR_8540 || ver == SVR_8560 || 626 ver == SVR_8541 || ver == SVR_8555) { 627 puts("128 KiB "); 628 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 629 cache_ctl = 0xc4000000; 630 } else { 631 puts("256 KiB "); 632 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 633 } 634 break; 635 case 0x2: 636 if (ver == SVR_8540 || ver == SVR_8560 || 637 ver == SVR_8541 || ver == SVR_8555) { 638 puts("256 KiB "); 639 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 640 cache_ctl = 0xc8000000; 641 } else { 642 puts("512 KiB "); 643 /* set L2E=1, L2I=1, & L2SRAM=0 */ 644 cache_ctl = 0xc0000000; 645 } 646 break; 647 case 0x3: 648 puts("1024 KiB "); 649 /* set L2E=1, L2I=1, & L2SRAM=0 */ 650 cache_ctl = 0xc0000000; 651 break; 652 } 653 654 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 655 puts("already enabled"); 656 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 657 u32 l2srbar = l2cache->l2srbar0; 658 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 659 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 660 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 661 l2cache->l2srbar0 = l2srbar; 662 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 663 } 664 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 665 puts("\n"); 666 } else { 667 asm("msync;isync"); 668 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 669 asm("msync;isync"); 670 puts("enabled\n"); 671 } 672 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 673 if (SVR_SOC_VER(svr) == SVR_P2040) { 674 puts("N/A\n"); 675 goto skip_l2; 676 } 677 678 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 679 680 /* invalidate the L2 cache */ 681 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 682 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 683 ; 684 685 #ifdef CONFIG_SYS_CACHE_STASHING 686 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 687 mtspr(SPRN_L2CSR1, (32 + 1)); 688 #endif 689 690 /* enable the cache */ 691 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 692 693 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 694 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 695 ; 696 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 697 } 698 699 skip_l2: 700 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 701 if (l2cache->l2csr0 & L2CSR0_L2E) 702 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 703 " enabled\n"); 704 705 enable_cluster_l2(); 706 #else 707 puts("disabled\n"); 708 #endif 709 710 return 0; 711 } 712 713 /* 714 * 715 * The newer 8548, etc, parts have twice as much cache, but 716 * use the same bit-encoding as the older 8555, etc, parts. 717 * 718 */ 719 int cpu_init_r(void) 720 { 721 __maybe_unused u32 svr = get_svr(); 722 #ifdef CONFIG_SYS_LBC_LCRR 723 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 724 #endif 725 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 726 extern int spin_table_compat; 727 const char *spin; 728 #endif 729 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 730 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 731 #endif 732 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 733 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 734 /* 735 * CPU22 and NMG_CPU_A011 share the same workaround. 736 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 737 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 738 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 739 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 740 * be disabled by hwconfig with syntax: 741 * 742 * fsl_cpu_a011:disable 743 */ 744 extern int enable_cpu_a011_workaround; 745 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 746 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 747 #else 748 char buffer[HWCONFIG_BUFFER_SIZE]; 749 char *buf = NULL; 750 int n, res; 751 752 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 753 if (n > 0) 754 buf = buffer; 755 756 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 757 if (res > 0) { 758 enable_cpu_a011_workaround = 0; 759 } else { 760 if (n >= HWCONFIG_BUFFER_SIZE) { 761 printf("fsl_cpu_a011 was not found. hwconfig variable " 762 "may be too long\n"); 763 } 764 enable_cpu_a011_workaround = 765 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 766 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 767 } 768 #endif 769 if (enable_cpu_a011_workaround) { 770 flush_dcache(); 771 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 772 sync(); 773 } 774 #endif 775 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 776 /* 777 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 778 * in write shadow mode. Checking DCWS before setting SPR 976. 779 */ 780 if (mfspr(L1CSR2) & L1CSR2_DCWS) 781 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 782 #endif 783 784 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 785 spin = getenv("spin_table_compat"); 786 if (spin && (*spin == 'n')) 787 spin_table_compat = 0; 788 else 789 spin_table_compat = 1; 790 #endif 791 792 l2cache_init(); 793 #if defined(CONFIG_RAMBOOT_PBL) 794 disable_cpc_sram(); 795 #endif 796 enable_cpc(); 797 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 798 enable_tdm_law(); 799 #endif 800 801 #ifndef CONFIG_SYS_FSL_NO_SERDES 802 /* needs to be in ram since code uses global static vars */ 803 fsl_serdes_init(); 804 #endif 805 806 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 807 #define MCFGR_AXIPIPE 0x000000f0 808 if (IS_SVR_REV(svr, 1, 0)) 809 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE); 810 #endif 811 812 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 813 if (IS_SVR_REV(svr, 1, 0)) { 814 int i; 815 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 816 817 for (i = 0; i < 12; i++) { 818 p += i + (i > 5 ? 11 : 0); 819 out_be32(p, 0x2); 820 } 821 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 822 out_be32(p, 0x34); 823 } 824 #endif 825 826 #ifdef CONFIG_SYS_SRIO 827 srio_init(); 828 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 829 char *s = getenv("bootmaster"); 830 if (s) { 831 if (!strcmp(s, "SRIO1")) { 832 srio_boot_master(1); 833 srio_boot_master_release_slave(1); 834 } 835 if (!strcmp(s, "SRIO2")) { 836 srio_boot_master(2); 837 srio_boot_master_release_slave(2); 838 } 839 } 840 #endif 841 #endif 842 843 #if defined(CONFIG_MP) 844 setup_mp(); 845 #endif 846 847 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 848 { 849 if (SVR_MAJ(svr) < 3) { 850 void *p; 851 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 852 setbits_be32(p, 1 << (31 - 14)); 853 } 854 } 855 #endif 856 857 #ifdef CONFIG_SYS_LBC_LCRR 858 /* 859 * Modify the CLKDIV field of LCRR register to improve the writing 860 * speed for NOR flash. 861 */ 862 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 863 __raw_readl(&lbc->lcrr); 864 isync(); 865 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 866 udelay(100); 867 #endif 868 #endif 869 870 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 871 { 872 struct ccsr_usb_phy __iomem *usb_phy1 = 873 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 874 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 875 if (has_erratum_a006261()) 876 fsl_erratum_a006261_workaround(usb_phy1); 877 #endif 878 out_be32(&usb_phy1->usb_enable_override, 879 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 880 } 881 #endif 882 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 883 { 884 struct ccsr_usb_phy __iomem *usb_phy2 = 885 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 886 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 887 if (has_erratum_a006261()) 888 fsl_erratum_a006261_workaround(usb_phy2); 889 #endif 890 out_be32(&usb_phy2->usb_enable_override, 891 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 892 } 893 #endif 894 895 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 896 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 897 * multi-bit ECC errors which has impact on performance, so software 898 * should disable all ECC reporting from USB1 and USB2. 899 */ 900 if (IS_SVR_REV(get_svr(), 1, 0)) { 901 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 902 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 903 setbits_be32(&dcfg->ecccr1, 904 (DCSR_DCFG_ECC_DISABLE_USB1 | 905 DCSR_DCFG_ECC_DISABLE_USB2)); 906 } 907 #endif 908 909 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 910 struct ccsr_usb_phy __iomem *usb_phy = 911 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 912 setbits_be32(&usb_phy->pllprg[1], 913 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 914 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 915 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 916 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 917 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 918 usb_single_source_clk_configure(usb_phy); 919 #endif 920 setbits_be32(&usb_phy->port1.ctrl, 921 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 922 setbits_be32(&usb_phy->port1.drvvbuscfg, 923 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 924 setbits_be32(&usb_phy->port1.pwrfltcfg, 925 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 926 setbits_be32(&usb_phy->port2.ctrl, 927 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 928 setbits_be32(&usb_phy->port2.drvvbuscfg, 929 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 930 setbits_be32(&usb_phy->port2.pwrfltcfg, 931 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 932 933 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 934 if (has_erratum_a006261()) 935 fsl_erratum_a006261_workaround(usb_phy); 936 #endif 937 938 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 939 940 #ifdef CONFIG_FMAN_ENET 941 fman_enet_init(); 942 #endif 943 944 #ifdef CONFIG_FSL_CAAM 945 sec_init(); 946 #endif 947 948 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 949 /* 950 * For P1022/1013 Rev1.0 silicon, after power on SATA host 951 * controller is configured in legacy mode instead of the 952 * expected enterprise mode. Software needs to clear bit[28] 953 * of HControl register to change to enterprise mode from 954 * legacy mode. We assume that the controller is offline. 955 */ 956 if (IS_SVR_REV(svr, 1, 0) && 957 ((SVR_SOC_VER(svr) == SVR_P1022) || 958 (SVR_SOC_VER(svr) == SVR_P1013))) { 959 fsl_sata_reg_t *reg; 960 961 /* first SATA controller */ 962 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 963 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 964 965 /* second SATA controller */ 966 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 967 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 968 } 969 #endif 970 971 init_used_tlb_cams(); 972 973 return 0; 974 } 975 976 void arch_preboot_os(void) 977 { 978 u32 msr; 979 980 /* 981 * We are changing interrupt offsets and are about to boot the OS so 982 * we need to make sure we disable all async interrupts. EE is already 983 * disabled by the time we get called. 984 */ 985 msr = mfmsr(); 986 msr &= ~(MSR_ME|MSR_CE); 987 mtmsr(msr); 988 } 989 990 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 991 int sata_initialize(void) 992 { 993 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 994 return __sata_initialize(); 995 996 return 1; 997 } 998 #endif 999 1000 void cpu_secondary_init_r(void) 1001 { 1002 #ifdef CONFIG_U_QE 1003 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 1004 #elif defined CONFIG_QE 1005 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 1006 #endif 1007 1008 #ifdef CONFIG_QE 1009 qe_init(qe_base); 1010 qe_reset(); 1011 #endif 1012 } 1013