1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <sata.h> 34 #include <asm/io.h> 35 #include <asm/cache.h> 36 #include <asm/mmu.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_serdes.h> 39 #include "mp.h" 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 extern void srio_init(void); 44 45 #ifdef CONFIG_QE 46 extern qe_iop_conf_t qe_iop_conf_tab[]; 47 extern void qe_config_iopin(u8 port, u8 pin, int dir, 48 int open_drain, int assign); 49 extern void qe_init(uint qe_base); 50 extern void qe_reset(void); 51 52 static void config_qe_ioports(void) 53 { 54 u8 port, pin; 55 int dir, open_drain, assign; 56 int i; 57 58 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 59 port = qe_iop_conf_tab[i].port; 60 pin = qe_iop_conf_tab[i].pin; 61 dir = qe_iop_conf_tab[i].dir; 62 open_drain = qe_iop_conf_tab[i].open_drain; 63 assign = qe_iop_conf_tab[i].assign; 64 qe_config_iopin(port, pin, dir, open_drain, assign); 65 } 66 } 67 #endif 68 69 #ifdef CONFIG_CPM2 70 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 71 { 72 int portnum; 73 74 for (portnum = 0; portnum < 4; portnum++) { 75 uint pmsk = 0, 76 ppar = 0, 77 psor = 0, 78 pdir = 0, 79 podr = 0, 80 pdat = 0; 81 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 82 iop_conf_t *eiopc = iopc + 32; 83 uint msk = 1; 84 85 /* 86 * NOTE: 87 * index 0 refers to pin 31, 88 * index 31 refers to pin 0 89 */ 90 while (iopc < eiopc) { 91 if (iopc->conf) { 92 pmsk |= msk; 93 if (iopc->ppar) 94 ppar |= msk; 95 if (iopc->psor) 96 psor |= msk; 97 if (iopc->pdir) 98 pdir |= msk; 99 if (iopc->podr) 100 podr |= msk; 101 if (iopc->pdat) 102 pdat |= msk; 103 } 104 105 msk <<= 1; 106 iopc++; 107 } 108 109 if (pmsk != 0) { 110 volatile ioport_t *iop = ioport_addr (cpm, portnum); 111 uint tpmsk = ~pmsk; 112 113 /* 114 * the (somewhat confused) paragraph at the 115 * bottom of page 35-5 warns that there might 116 * be "unknown behaviour" when programming 117 * PSORx and PDIRx, if PPARx = 1, so I 118 * decided this meant I had to disable the 119 * dedicated function first, and enable it 120 * last. 121 */ 122 iop->ppar &= tpmsk; 123 iop->psor = (iop->psor & tpmsk) | psor; 124 iop->podr = (iop->podr & tpmsk) | podr; 125 iop->pdat = (iop->pdat & tpmsk) | pdat; 126 iop->pdir = (iop->pdir & tpmsk) | pdir; 127 iop->ppar |= ppar; 128 } 129 } 130 } 131 #endif 132 133 #ifdef CONFIG_SYS_FSL_CPC 134 static void enable_cpc(void) 135 { 136 int i; 137 u32 size = 0; 138 139 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 140 141 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 142 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 143 size += CPC_CFG0_SZ_K(cpccfg0); 144 145 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 146 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 147 #endif 148 149 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 150 /* Read back to sync write */ 151 in_be32(&cpc->cpccsr0); 152 153 } 154 155 printf("Corenet Platform Cache: %d KB enabled\n", size); 156 } 157 158 void invalidate_cpc(void) 159 { 160 int i; 161 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 162 163 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 164 /* Flash invalidate the CPC and clear all the locks */ 165 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 166 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 167 ; 168 } 169 } 170 #else 171 #define enable_cpc() 172 #define invalidate_cpc() 173 #endif /* CONFIG_SYS_FSL_CPC */ 174 175 /* 176 * Breathe some life into the CPU... 177 * 178 * Set up the memory map 179 * initialize a bunch of registers 180 */ 181 182 #ifdef CONFIG_FSL_CORENET 183 static void corenet_tb_init(void) 184 { 185 volatile ccsr_rcpm_t *rcpm = 186 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 187 volatile ccsr_pic_t *pic = 188 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 189 u32 whoami = in_be32(&pic->whoami); 190 191 /* Enable the timebase register for this core */ 192 out_be32(&rcpm->ctbenrl, (1 << whoami)); 193 } 194 #endif 195 196 void cpu_init_f (void) 197 { 198 extern void m8560_cpm_reset (void); 199 #ifdef CONFIG_MPC8548 200 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 201 uint svr = get_svr(); 202 203 /* 204 * CPU2 errata workaround: A core hang possible while executing 205 * a msync instruction and a snoopable transaction from an I/O 206 * master tagged to make quick forward progress is present. 207 * Fixed in silicon rev 2.1. 208 */ 209 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 210 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 211 #endif 212 213 disable_tlb(14); 214 disable_tlb(15); 215 216 #ifdef CONFIG_CPM2 217 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 218 #endif 219 220 init_early_memctl_regs(); 221 222 #if defined(CONFIG_CPM2) 223 m8560_cpm_reset(); 224 #endif 225 #ifdef CONFIG_QE 226 /* Config QE ioports */ 227 config_qe_ioports(); 228 #endif 229 #if defined(CONFIG_FSL_DMA) 230 dma_init(); 231 #endif 232 #ifdef CONFIG_FSL_CORENET 233 corenet_tb_init(); 234 #endif 235 init_used_tlb_cams(); 236 237 /* Invalidate the CPC before DDR gets enabled */ 238 invalidate_cpc(); 239 } 240 241 /* Implement a dummy function for those platforms w/o SERDES */ 242 static void __fsl_serdes__init(void) 243 { 244 return ; 245 } 246 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 247 248 /* 249 * Initialize L2 as cache. 250 * 251 * The newer 8548, etc, parts have twice as much cache, but 252 * use the same bit-encoding as the older 8555, etc, parts. 253 * 254 */ 255 int cpu_init_r(void) 256 { 257 #ifdef CONFIG_SYS_LBC_LCRR 258 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 259 #endif 260 261 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) 262 flush_dcache(); 263 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 264 sync(); 265 #endif 266 267 puts ("L2: "); 268 269 #if defined(CONFIG_L2_CACHE) 270 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 271 volatile uint cache_ctl; 272 uint svr, ver; 273 uint l2srbar; 274 u32 l2siz_field; 275 276 svr = get_svr(); 277 ver = SVR_SOC_VER(svr); 278 279 asm("msync;isync"); 280 cache_ctl = l2cache->l2ctl; 281 282 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 283 if (cache_ctl & MPC85xx_L2CTL_L2E) { 284 /* Clear L2 SRAM memory-mapped base address */ 285 out_be32(&l2cache->l2srbar0, 0x0); 286 out_be32(&l2cache->l2srbar1, 0x0); 287 288 /* set MBECCDIS=0, SBECCDIS=0 */ 289 clrbits_be32(&l2cache->l2errdis, 290 (MPC85xx_L2ERRDIS_MBECC | 291 MPC85xx_L2ERRDIS_SBECC)); 292 293 /* set L2E=0, L2SRAM=0 */ 294 clrbits_be32(&l2cache->l2ctl, 295 (MPC85xx_L2CTL_L2E | 296 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 297 } 298 #endif 299 300 l2siz_field = (cache_ctl >> 28) & 0x3; 301 302 switch (l2siz_field) { 303 case 0x0: 304 printf(" unknown size (0x%08x)\n", cache_ctl); 305 return -1; 306 break; 307 case 0x1: 308 if (ver == SVR_8540 || ver == SVR_8560 || 309 ver == SVR_8541 || ver == SVR_8541_E || 310 ver == SVR_8555 || ver == SVR_8555_E) { 311 puts("128 KB "); 312 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 313 cache_ctl = 0xc4000000; 314 } else { 315 puts("256 KB "); 316 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 317 } 318 break; 319 case 0x2: 320 if (ver == SVR_8540 || ver == SVR_8560 || 321 ver == SVR_8541 || ver == SVR_8541_E || 322 ver == SVR_8555 || ver == SVR_8555_E) { 323 puts("256 KB "); 324 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 325 cache_ctl = 0xc8000000; 326 } else { 327 puts ("512 KB "); 328 /* set L2E=1, L2I=1, & L2SRAM=0 */ 329 cache_ctl = 0xc0000000; 330 } 331 break; 332 case 0x3: 333 puts("1024 KB "); 334 /* set L2E=1, L2I=1, & L2SRAM=0 */ 335 cache_ctl = 0xc0000000; 336 break; 337 } 338 339 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 340 puts("already enabled"); 341 l2srbar = l2cache->l2srbar0; 342 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 343 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 344 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 345 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 346 l2cache->l2srbar0 = l2srbar; 347 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 348 } 349 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 350 puts("\n"); 351 } else { 352 asm("msync;isync"); 353 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 354 asm("msync;isync"); 355 puts("enabled\n"); 356 } 357 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 358 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 359 360 /* invalidate the L2 cache */ 361 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 362 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 363 ; 364 365 #ifdef CONFIG_SYS_CACHE_STASHING 366 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 367 mtspr(SPRN_L2CSR1, (32 + 1)); 368 #endif 369 370 /* enable the cache */ 371 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 372 373 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 374 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 375 ; 376 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 377 } 378 #else 379 puts("disabled\n"); 380 #endif 381 382 enable_cpc(); 383 384 #ifdef CONFIG_QE 385 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 386 qe_init(qe_base); 387 qe_reset(); 388 #endif 389 390 /* needs to be in ram since code uses global static vars */ 391 fsl_serdes_init(); 392 393 #ifdef CONFIG_SYS_SRIO 394 srio_init(); 395 #endif 396 397 #if defined(CONFIG_MP) 398 setup_mp(); 399 #endif 400 401 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136 402 { 403 void *p; 404 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 405 setbits_be32(p, 1 << (31 - 14)); 406 } 407 #endif 408 409 #ifdef CONFIG_SYS_LBC_LCRR 410 /* 411 * Modify the CLKDIV field of LCRR register to improve the writing 412 * speed for NOR flash. 413 */ 414 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 415 __raw_readl(&lbc->lcrr); 416 isync(); 417 #endif 418 419 return 0; 420 } 421 422 extern void setup_ivors(void); 423 424 void arch_preboot_os(void) 425 { 426 u32 msr; 427 428 /* 429 * We are changing interrupt offsets and are about to boot the OS so 430 * we need to make sure we disable all async interrupts. EE is already 431 * disabled by the time we get called. 432 */ 433 msr = mfmsr(); 434 msr &= ~(MSR_ME|MSR_CE|MSR_DE); 435 mtmsr(msr); 436 437 setup_ivors(); 438 } 439 440 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 441 int sata_initialize(void) 442 { 443 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 444 return __sata_initialize(); 445 446 return 1; 447 } 448 #endif 449