1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <asm/fsl_law.h> 23 #include <asm/fsl_serdes.h> 24 #include <asm/fsl_srio.h> 25 #include <fsl_usb.h> 26 #include <hwconfig.h> 27 #include <linux/compiler.h> 28 #include "mp.h" 29 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 30 #include <nand.h> 31 #include <errno.h> 32 #endif 33 34 #include "../../../../drivers/block/fsl_sata.h" 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #ifdef CONFIG_QE 39 extern qe_iop_conf_t qe_iop_conf_tab[]; 40 extern void qe_config_iopin(u8 port, u8 pin, int dir, 41 int open_drain, int assign); 42 extern void qe_init(uint qe_base); 43 extern void qe_reset(void); 44 45 static void config_qe_ioports(void) 46 { 47 u8 port, pin; 48 int dir, open_drain, assign; 49 int i; 50 51 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 52 port = qe_iop_conf_tab[i].port; 53 pin = qe_iop_conf_tab[i].pin; 54 dir = qe_iop_conf_tab[i].dir; 55 open_drain = qe_iop_conf_tab[i].open_drain; 56 assign = qe_iop_conf_tab[i].assign; 57 qe_config_iopin(port, pin, dir, open_drain, assign); 58 } 59 } 60 #endif 61 62 #ifdef CONFIG_CPM2 63 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 64 { 65 int portnum; 66 67 for (portnum = 0; portnum < 4; portnum++) { 68 uint pmsk = 0, 69 ppar = 0, 70 psor = 0, 71 pdir = 0, 72 podr = 0, 73 pdat = 0; 74 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 75 iop_conf_t *eiopc = iopc + 32; 76 uint msk = 1; 77 78 /* 79 * NOTE: 80 * index 0 refers to pin 31, 81 * index 31 refers to pin 0 82 */ 83 while (iopc < eiopc) { 84 if (iopc->conf) { 85 pmsk |= msk; 86 if (iopc->ppar) 87 ppar |= msk; 88 if (iopc->psor) 89 psor |= msk; 90 if (iopc->pdir) 91 pdir |= msk; 92 if (iopc->podr) 93 podr |= msk; 94 if (iopc->pdat) 95 pdat |= msk; 96 } 97 98 msk <<= 1; 99 iopc++; 100 } 101 102 if (pmsk != 0) { 103 volatile ioport_t *iop = ioport_addr (cpm, portnum); 104 uint tpmsk = ~pmsk; 105 106 /* 107 * the (somewhat confused) paragraph at the 108 * bottom of page 35-5 warns that there might 109 * be "unknown behaviour" when programming 110 * PSORx and PDIRx, if PPARx = 1, so I 111 * decided this meant I had to disable the 112 * dedicated function first, and enable it 113 * last. 114 */ 115 iop->ppar &= tpmsk; 116 iop->psor = (iop->psor & tpmsk) | psor; 117 iop->podr = (iop->podr & tpmsk) | podr; 118 iop->pdat = (iop->pdat & tpmsk) | pdat; 119 iop->pdir = (iop->pdir & tpmsk) | pdir; 120 iop->ppar |= ppar; 121 } 122 } 123 } 124 #endif 125 126 #ifdef CONFIG_SYS_FSL_CPC 127 static void enable_cpc(void) 128 { 129 int i; 130 u32 size = 0; 131 132 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 133 134 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 135 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 136 size += CPC_CFG0_SZ_K(cpccfg0); 137 #ifdef CONFIG_RAMBOOT_PBL 138 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 139 /* find and disable LAW of SRAM */ 140 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 141 142 if (law.index == -1) { 143 printf("\nFatal error happened\n"); 144 return; 145 } 146 disable_law(law.index); 147 148 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 149 out_be32(&cpc->cpccsr0, 0); 150 out_be32(&cpc->cpcsrcr0, 0); 151 } 152 #endif 153 154 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 155 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 156 #endif 157 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 158 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 159 #endif 160 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 161 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 162 #endif 163 164 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 165 /* Read back to sync write */ 166 in_be32(&cpc->cpccsr0); 167 168 } 169 170 puts("Corenet Platform Cache: "); 171 print_size(size * 1024, " enabled\n"); 172 } 173 174 static void invalidate_cpc(void) 175 { 176 int i; 177 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 178 179 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 180 /* skip CPC when it used as all SRAM */ 181 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 182 continue; 183 /* Flash invalidate the CPC and clear all the locks */ 184 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 185 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 186 ; 187 } 188 } 189 #else 190 #define enable_cpc() 191 #define invalidate_cpc() 192 #endif /* CONFIG_SYS_FSL_CPC */ 193 194 /* 195 * Breathe some life into the CPU... 196 * 197 * Set up the memory map 198 * initialize a bunch of registers 199 */ 200 201 #ifdef CONFIG_FSL_CORENET 202 static void corenet_tb_init(void) 203 { 204 volatile ccsr_rcpm_t *rcpm = 205 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 206 volatile ccsr_pic_t *pic = 207 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 208 u32 whoami = in_be32(&pic->whoami); 209 210 /* Enable the timebase register for this core */ 211 out_be32(&rcpm->ctbenrl, (1 << whoami)); 212 } 213 #endif 214 215 void cpu_init_f (void) 216 { 217 extern void m8560_cpm_reset (void); 218 #ifdef CONFIG_SYS_DCSRBAR_PHYS 219 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 220 #endif 221 #if defined(CONFIG_SECURE_BOOT) 222 struct law_entry law; 223 #endif 224 #ifdef CONFIG_MPC8548 225 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 226 uint svr = get_svr(); 227 228 /* 229 * CPU2 errata workaround: A core hang possible while executing 230 * a msync instruction and a snoopable transaction from an I/O 231 * master tagged to make quick forward progress is present. 232 * Fixed in silicon rev 2.1. 233 */ 234 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 235 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 236 #endif 237 238 disable_tlb(14); 239 disable_tlb(15); 240 241 #if defined(CONFIG_SECURE_BOOT) 242 /* Disable the LAW created for NOR flash by the PBI commands */ 243 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 244 if (law.index != -1) 245 disable_law(law.index); 246 #endif 247 248 #ifdef CONFIG_CPM2 249 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 250 #endif 251 252 init_early_memctl_regs(); 253 254 #if defined(CONFIG_CPM2) 255 m8560_cpm_reset(); 256 #endif 257 #ifdef CONFIG_QE 258 /* Config QE ioports */ 259 config_qe_ioports(); 260 #endif 261 #if defined(CONFIG_FSL_DMA) 262 dma_init(); 263 #endif 264 #ifdef CONFIG_FSL_CORENET 265 corenet_tb_init(); 266 #endif 267 init_used_tlb_cams(); 268 269 /* Invalidate the CPC before DDR gets enabled */ 270 invalidate_cpc(); 271 272 #ifdef CONFIG_SYS_DCSRBAR_PHYS 273 /* set DCSRCR so that DCSR space is 1G */ 274 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 275 in_be32(&gur->dcsrcr); 276 #endif 277 278 } 279 280 /* Implement a dummy function for those platforms w/o SERDES */ 281 static void __fsl_serdes__init(void) 282 { 283 return ; 284 } 285 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 286 287 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 288 int enable_cluster_l2(void) 289 { 290 int i = 0; 291 u32 cluster; 292 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 293 struct ccsr_cluster_l2 __iomem *l2cache; 294 295 cluster = in_be32(&gur->tp_cluster[i].lower); 296 if (cluster & TP_CLUSTER_EOC) 297 return 0; 298 299 /* The first cache has already been set up, so skip it */ 300 i++; 301 302 /* Look through the remaining clusters, and set up their caches */ 303 do { 304 int j, cluster_valid = 0; 305 306 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 307 308 cluster = in_be32(&gur->tp_cluster[i].lower); 309 310 /* check that at least one core/accel is enabled in cluster */ 311 for (j = 0; j < 4; j++) { 312 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 313 u32 type = in_be32(&gur->tp_ityp[idx]); 314 315 if (type & TP_ITYP_AV) 316 cluster_valid = 1; 317 } 318 319 if (cluster_valid) { 320 /* set stash ID to (cluster) * 2 + 32 + 1 */ 321 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 322 323 printf("enable l2 for cluster %d %p\n", i, l2cache); 324 325 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 326 while ((in_be32(&l2cache->l2csr0) 327 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 328 ; 329 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 330 } 331 i++; 332 } while (!(cluster & TP_CLUSTER_EOC)); 333 334 return 0; 335 } 336 #endif 337 338 /* 339 * Initialize L2 as cache. 340 * 341 * The newer 8548, etc, parts have twice as much cache, but 342 * use the same bit-encoding as the older 8555, etc, parts. 343 * 344 */ 345 int cpu_init_r(void) 346 { 347 __maybe_unused u32 svr = get_svr(); 348 #ifdef CONFIG_SYS_LBC_LCRR 349 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 350 #endif 351 #ifdef CONFIG_L2_CACHE 352 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 353 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 354 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 355 #endif 356 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 357 extern int spin_table_compat; 358 const char *spin; 359 #endif 360 361 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 362 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 363 /* 364 * CPU22 and NMG_CPU_A011 share the same workaround. 365 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 366 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 367 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 368 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 369 * be disabled by hwconfig with syntax: 370 * 371 * fsl_cpu_a011:disable 372 */ 373 extern int enable_cpu_a011_workaround; 374 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 375 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 376 #else 377 char buffer[HWCONFIG_BUFFER_SIZE]; 378 char *buf = NULL; 379 int n, res; 380 381 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 382 if (n > 0) 383 buf = buffer; 384 385 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 386 if (res > 0) 387 enable_cpu_a011_workaround = 0; 388 else { 389 if (n >= HWCONFIG_BUFFER_SIZE) { 390 printf("fsl_cpu_a011 was not found. hwconfig variable " 391 "may be too long\n"); 392 } 393 enable_cpu_a011_workaround = 394 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 395 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 396 } 397 #endif 398 if (enable_cpu_a011_workaround) { 399 flush_dcache(); 400 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 401 sync(); 402 } 403 #endif 404 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 405 /* 406 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 407 * in write shadow mode. Checking DCWS before setting SPR 976. 408 */ 409 if (mfspr(L1CSR2) & L1CSR2_DCWS) 410 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 411 #endif 412 413 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 414 spin = getenv("spin_table_compat"); 415 if (spin && (*spin == 'n')) 416 spin_table_compat = 0; 417 else 418 spin_table_compat = 1; 419 #endif 420 421 puts ("L2: "); 422 423 #if defined(CONFIG_L2_CACHE) 424 volatile uint cache_ctl; 425 uint ver; 426 u32 l2siz_field; 427 428 ver = SVR_SOC_VER(svr); 429 430 asm("msync;isync"); 431 cache_ctl = l2cache->l2ctl; 432 433 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 434 if (cache_ctl & MPC85xx_L2CTL_L2E) { 435 /* Clear L2 SRAM memory-mapped base address */ 436 out_be32(&l2cache->l2srbar0, 0x0); 437 out_be32(&l2cache->l2srbar1, 0x0); 438 439 /* set MBECCDIS=0, SBECCDIS=0 */ 440 clrbits_be32(&l2cache->l2errdis, 441 (MPC85xx_L2ERRDIS_MBECC | 442 MPC85xx_L2ERRDIS_SBECC)); 443 444 /* set L2E=0, L2SRAM=0 */ 445 clrbits_be32(&l2cache->l2ctl, 446 (MPC85xx_L2CTL_L2E | 447 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 448 } 449 #endif 450 451 l2siz_field = (cache_ctl >> 28) & 0x3; 452 453 switch (l2siz_field) { 454 case 0x0: 455 printf(" unknown size (0x%08x)\n", cache_ctl); 456 return -1; 457 break; 458 case 0x1: 459 if (ver == SVR_8540 || ver == SVR_8560 || 460 ver == SVR_8541 || ver == SVR_8555) { 461 puts("128 KiB "); 462 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 463 cache_ctl = 0xc4000000; 464 } else { 465 puts("256 KiB "); 466 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 467 } 468 break; 469 case 0x2: 470 if (ver == SVR_8540 || ver == SVR_8560 || 471 ver == SVR_8541 || ver == SVR_8555) { 472 puts("256 KiB "); 473 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 474 cache_ctl = 0xc8000000; 475 } else { 476 puts("512 KiB "); 477 /* set L2E=1, L2I=1, & L2SRAM=0 */ 478 cache_ctl = 0xc0000000; 479 } 480 break; 481 case 0x3: 482 puts("1024 KiB "); 483 /* set L2E=1, L2I=1, & L2SRAM=0 */ 484 cache_ctl = 0xc0000000; 485 break; 486 } 487 488 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 489 puts("already enabled"); 490 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 491 u32 l2srbar = l2cache->l2srbar0; 492 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 493 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 494 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 495 l2cache->l2srbar0 = l2srbar; 496 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 497 } 498 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 499 puts("\n"); 500 } else { 501 asm("msync;isync"); 502 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 503 asm("msync;isync"); 504 puts("enabled\n"); 505 } 506 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 507 if (SVR_SOC_VER(svr) == SVR_P2040) { 508 puts("N/A\n"); 509 goto skip_l2; 510 } 511 512 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 513 514 /* invalidate the L2 cache */ 515 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 516 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 517 ; 518 519 #ifdef CONFIG_SYS_CACHE_STASHING 520 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 521 mtspr(SPRN_L2CSR1, (32 + 1)); 522 #endif 523 524 /* enable the cache */ 525 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 526 527 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 528 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 529 ; 530 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 531 } 532 533 skip_l2: 534 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 535 if (l2cache->l2csr0 & L2CSR0_L2E) 536 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 537 " enabled\n"); 538 539 enable_cluster_l2(); 540 #else 541 puts("disabled\n"); 542 #endif 543 544 enable_cpc(); 545 546 #ifndef CONFIG_SYS_FSL_NO_SERDES 547 /* needs to be in ram since code uses global static vars */ 548 fsl_serdes_init(); 549 #endif 550 551 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 552 if (IS_SVR_REV(svr, 1, 0)) { 553 int i; 554 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 555 556 for (i = 0; i < 12; i++) { 557 p += i + (i > 5 ? 11 : 0); 558 out_be32(p, 0x2); 559 } 560 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 561 out_be32(p, 0x34); 562 } 563 #endif 564 565 #ifdef CONFIG_SYS_SRIO 566 srio_init(); 567 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 568 char *s = getenv("bootmaster"); 569 if (s) { 570 if (!strcmp(s, "SRIO1")) { 571 srio_boot_master(1); 572 srio_boot_master_release_slave(1); 573 } 574 if (!strcmp(s, "SRIO2")) { 575 srio_boot_master(2); 576 srio_boot_master_release_slave(2); 577 } 578 } 579 #endif 580 #endif 581 582 #if defined(CONFIG_MP) 583 setup_mp(); 584 #endif 585 586 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 587 { 588 if (SVR_MAJ(svr) < 3) { 589 void *p; 590 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 591 setbits_be32(p, 1 << (31 - 14)); 592 } 593 } 594 #endif 595 596 #ifdef CONFIG_SYS_LBC_LCRR 597 /* 598 * Modify the CLKDIV field of LCRR register to improve the writing 599 * speed for NOR flash. 600 */ 601 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 602 __raw_readl(&lbc->lcrr); 603 isync(); 604 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 605 udelay(100); 606 #endif 607 #endif 608 609 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 610 { 611 struct ccsr_usb_phy __iomem *usb_phy1 = 612 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 613 out_be32(&usb_phy1->usb_enable_override, 614 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 615 } 616 #endif 617 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 618 { 619 struct ccsr_usb_phy __iomem *usb_phy2 = 620 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 621 out_be32(&usb_phy2->usb_enable_override, 622 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 623 } 624 #endif 625 626 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 627 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 628 * multi-bit ECC errors which has impact on performance, so software 629 * should disable all ECC reporting from USB1 and USB2. 630 */ 631 if (IS_SVR_REV(get_svr(), 1, 0)) { 632 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 633 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 634 setbits_be32(&dcfg->ecccr1, 635 (DCSR_DCFG_ECC_DISABLE_USB1 | 636 DCSR_DCFG_ECC_DISABLE_USB2)); 637 } 638 #endif 639 640 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 641 struct ccsr_usb_phy __iomem *usb_phy = 642 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 643 setbits_be32(&usb_phy->pllprg[1], 644 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 645 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 646 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 647 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 648 setbits_be32(&usb_phy->port1.ctrl, 649 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 650 setbits_be32(&usb_phy->port1.drvvbuscfg, 651 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 652 setbits_be32(&usb_phy->port1.pwrfltcfg, 653 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 654 setbits_be32(&usb_phy->port2.ctrl, 655 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 656 setbits_be32(&usb_phy->port2.drvvbuscfg, 657 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 658 setbits_be32(&usb_phy->port2.pwrfltcfg, 659 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 660 #endif 661 662 #ifdef CONFIG_FMAN_ENET 663 fman_enet_init(); 664 #endif 665 666 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 667 /* 668 * For P1022/1013 Rev1.0 silicon, after power on SATA host 669 * controller is configured in legacy mode instead of the 670 * expected enterprise mode. Software needs to clear bit[28] 671 * of HControl register to change to enterprise mode from 672 * legacy mode. We assume that the controller is offline. 673 */ 674 if (IS_SVR_REV(svr, 1, 0) && 675 ((SVR_SOC_VER(svr) == SVR_P1022) || 676 (SVR_SOC_VER(svr) == SVR_P1013))) { 677 fsl_sata_reg_t *reg; 678 679 /* first SATA controller */ 680 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 681 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 682 683 /* second SATA controller */ 684 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 685 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 686 } 687 #endif 688 689 690 return 0; 691 } 692 693 extern void setup_ivors(void); 694 695 void arch_preboot_os(void) 696 { 697 u32 msr; 698 699 /* 700 * We are changing interrupt offsets and are about to boot the OS so 701 * we need to make sure we disable all async interrupts. EE is already 702 * disabled by the time we get called. 703 */ 704 msr = mfmsr(); 705 msr &= ~(MSR_ME|MSR_CE); 706 mtmsr(msr); 707 708 setup_ivors(); 709 } 710 711 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 712 int sata_initialize(void) 713 { 714 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 715 return __sata_initialize(); 716 717 return 1; 718 } 719 #endif 720 721 void cpu_secondary_init_r(void) 722 { 723 #ifdef CONFIG_QE 724 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 725 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 726 int ret; 727 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 728 729 /* load QE firmware from NAND flash to DDR first */ 730 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 731 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); 732 733 if (ret && ret == -EUCLEAN) { 734 printf ("NAND read for QE firmware at offset %x failed %d\n", 735 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 736 } 737 #endif 738 qe_init(qe_base); 739 qe_reset(); 740 #endif 741 } 742