1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_ifc.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_lbc.h> 39 #include <post.h> 40 #include <asm/processor.h> 41 #include <asm/fsl_ddr_sdram.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 /* 46 * Default board reset function 47 */ 48 static void 49 __board_reset(void) 50 { 51 /* Do nothing */ 52 } 53 void board_reset(void) __attribute__((weak, alias("__board_reset"))); 54 55 int checkcpu (void) 56 { 57 sys_info_t sysinfo; 58 uint pvr, svr; 59 uint ver; 60 uint major, minor; 61 struct cpu_type *cpu; 62 char buf1[32], buf2[32]; 63 #if defined(CONFIG_DDR_CLK_FREQ) || \ 64 (defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)) 65 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 66 #endif /* CONFIG_FSL_CORENET */ 67 #ifdef CONFIG_DDR_CLK_FREQ 68 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 69 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 70 #else 71 #ifdef CONFIG_FSL_CORENET 72 u32 ddr_sync ; 73 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 74 ddr_sync = 0; /* only async mode is supported */ 75 #else 76 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 77 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 78 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 79 #else 80 u32 ddr_ratio = 0; 81 #endif /* CONFIG_FSL_CORENET */ 82 #endif /* CONFIG_DDR_CLK_FREQ */ 83 unsigned int i, core, nr_cores = cpu_numcores(); 84 u32 mask = cpu_mask(); 85 86 svr = get_svr(); 87 major = SVR_MAJ(svr); 88 minor = SVR_MIN(svr); 89 90 if (cpu_numcores() > 1) { 91 #ifndef CONFIG_MP 92 puts("Unicore software on multiprocessor system!!\n" 93 "To enable mutlticore build define CONFIG_MP\n"); 94 #endif 95 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 96 printf("CPU%d: ", pic->whoami); 97 } else { 98 puts("CPU: "); 99 } 100 101 cpu = gd->cpu; 102 103 puts(cpu->name); 104 if (IS_E_PROCESSOR(svr)) 105 puts("E"); 106 107 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 108 109 pvr = get_pvr(); 110 ver = PVR_VER(pvr); 111 major = PVR_MAJ(pvr); 112 minor = PVR_MIN(pvr); 113 114 printf("Core: "); 115 switch(ver) { 116 case PVR_VER_E500_V1: 117 case PVR_VER_E500_V2: 118 puts("E500"); 119 break; 120 case PVR_VER_E500MC: 121 puts("E500MC"); 122 break; 123 case PVR_VER_E5500: 124 puts("E5500"); 125 break; 126 case PVR_VER_E6500: 127 puts("E6500"); 128 break; 129 default: 130 puts("Unknown"); 131 break; 132 } 133 134 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 135 136 if (nr_cores > CONFIG_MAX_CPUS) { 137 panic("\nUnexpected number of cores: %d, max is %d\n", 138 nr_cores, CONFIG_MAX_CPUS); 139 } 140 141 get_sys_info(&sysinfo); 142 143 puts("Clock Configuration:"); 144 for_each_cpu(i, core, nr_cores, mask) { 145 if (!(i & 3)) 146 printf ("\n "); 147 printf("CPU%d:%-4s MHz, ", core, 148 strmhz(buf1, sysinfo.freqProcessor[core])); 149 } 150 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 151 152 #ifdef CONFIG_FSL_CORENET 153 if (ddr_sync == 1) { 154 printf(" DDR:%-4s MHz (%s MT/s data rate) " 155 "(Synchronous), ", 156 strmhz(buf1, sysinfo.freqDDRBus/2), 157 strmhz(buf2, sysinfo.freqDDRBus)); 158 } else { 159 printf(" DDR:%-4s MHz (%s MT/s data rate) " 160 "(Asynchronous), ", 161 strmhz(buf1, sysinfo.freqDDRBus/2), 162 strmhz(buf2, sysinfo.freqDDRBus)); 163 } 164 #else 165 switch (ddr_ratio) { 166 case 0x0: 167 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 168 strmhz(buf1, sysinfo.freqDDRBus/2), 169 strmhz(buf2, sysinfo.freqDDRBus)); 170 break; 171 case 0x7: 172 printf(" DDR:%-4s MHz (%s MT/s data rate) " 173 "(Synchronous), ", 174 strmhz(buf1, sysinfo.freqDDRBus/2), 175 strmhz(buf2, sysinfo.freqDDRBus)); 176 break; 177 default: 178 printf(" DDR:%-4s MHz (%s MT/s data rate) " 179 "(Asynchronous), ", 180 strmhz(buf1, sysinfo.freqDDRBus/2), 181 strmhz(buf2, sysinfo.freqDDRBus)); 182 break; 183 } 184 #endif 185 186 #if defined(CONFIG_FSL_LBC) 187 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 188 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 189 } else { 190 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 191 sysinfo.freqLocalBus); 192 } 193 #endif 194 195 #if defined(CONFIG_FSL_IFC) 196 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 197 #endif 198 199 #ifdef CONFIG_CPM2 200 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 201 #endif 202 203 #ifdef CONFIG_QE 204 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 205 #endif 206 207 #ifdef CONFIG_SYS_DPAA_FMAN 208 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 209 printf(" FMAN%d: %s MHz\n", i + 1, 210 strmhz(buf1, sysinfo.freqFMan[i])); 211 } 212 #endif 213 214 #ifdef CONFIG_SYS_DPAA_PME 215 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 216 #endif 217 218 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 219 220 return 0; 221 } 222 223 224 /* ------------------------------------------------------------------------- */ 225 226 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 227 { 228 /* Everything after the first generation of PQ3 parts has RSTCR */ 229 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 230 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 231 unsigned long val, msr; 232 233 /* 234 * Initiate hard reset in debug control register DBCR0 235 * Make sure MSR[DE] = 1. This only resets the core. 236 */ 237 msr = mfmsr (); 238 msr |= MSR_DE; 239 mtmsr (msr); 240 241 val = mfspr(DBCR0); 242 val |= 0x70000000; 243 mtspr(DBCR0,val); 244 #else 245 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 246 247 /* Attempt board-specific reset */ 248 board_reset(); 249 250 /* Next try asserting HRESET_REQ */ 251 out_be32(&gur->rstcr, 0x2); 252 udelay(100); 253 #endif 254 255 return 1; 256 } 257 258 259 /* 260 * Get timebase clock frequency 261 */ 262 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 263 #define CONFIG_SYS_FSL_TBCLK_DIV 8 264 #endif 265 unsigned long get_tbclk (void) 266 { 267 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 268 269 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 270 } 271 272 273 #if defined(CONFIG_WATCHDOG) 274 void 275 watchdog_reset(void) 276 { 277 int re_enable = disable_interrupts(); 278 reset_85xx_watchdog(); 279 if (re_enable) enable_interrupts(); 280 } 281 282 void 283 reset_85xx_watchdog(void) 284 { 285 /* 286 * Clear TSR(WIS) bit by writing 1 287 */ 288 mtspr(SPRN_TSR, TSR_WIS); 289 } 290 #endif /* CONFIG_WATCHDOG */ 291 292 /* 293 * Initializes on-chip MMC controllers. 294 * to override, implement board_mmc_init() 295 */ 296 int cpu_mmc_init(bd_t *bis) 297 { 298 #ifdef CONFIG_FSL_ESDHC 299 return fsl_esdhc_mmc_init(bis); 300 #else 301 return 0; 302 #endif 303 } 304 305 /* 306 * Print out the state of various machine registers. 307 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 308 * parameters for IFC and TLBs 309 */ 310 void mpc85xx_reginfo(void) 311 { 312 print_tlbcam(); 313 print_laws(); 314 #if defined(CONFIG_FSL_LBC) 315 print_lbc_regs(); 316 #endif 317 #ifdef CONFIG_FSL_IFC 318 print_ifc_regs(); 319 #endif 320 321 } 322 323 /* Common ddr init for non-corenet fsl 85xx platforms */ 324 #ifndef CONFIG_FSL_CORENET 325 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) 326 phys_size_t initdram(int board_type) 327 { 328 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 329 return fsl_ddr_sdram_size(); 330 #else 331 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 332 #endif 333 } 334 #else /* CONFIG_SYS_RAMBOOT */ 335 phys_size_t initdram(int board_type) 336 { 337 phys_size_t dram_size = 0; 338 339 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 340 { 341 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 342 unsigned int x = 10; 343 unsigned int i; 344 345 /* 346 * Work around to stabilize DDR DLL 347 */ 348 out_be32(&gur->ddrdllcr, 0x81000000); 349 asm("sync;isync;msync"); 350 udelay(200); 351 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 352 setbits_be32(&gur->devdisr, 0x00010000); 353 for (i = 0; i < x; i++) 354 ; 355 clrbits_be32(&gur->devdisr, 0x00010000); 356 x++; 357 } 358 } 359 #endif 360 361 #if defined(CONFIG_SPD_EEPROM) || \ 362 defined(CONFIG_DDR_SPD) || \ 363 defined(CONFIG_SYS_DDR_RAW_TIMING) 364 dram_size = fsl_ddr_sdram(); 365 #else 366 dram_size = fixed_sdram(); 367 #endif 368 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 369 dram_size *= 0x100000; 370 371 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 372 /* 373 * Initialize and enable DDR ECC. 374 */ 375 ddr_enable_ecc(dram_size); 376 #endif 377 378 #if defined(CONFIG_FSL_LBC) 379 /* Some boards also have sdram on the lbc */ 380 lbc_sdram_init(); 381 #endif 382 383 debug("DDR: "); 384 return dram_size; 385 } 386 #endif /* CONFIG_SYS_RAMBOOT */ 387 #endif 388 389 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 390 391 /* Board-specific functions defined in each board's ddr.c */ 392 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 393 unsigned int ctrl_num); 394 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 395 phys_addr_t *rpn); 396 unsigned int 397 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 398 399 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 400 401 static void dump_spd_ddr_reg(void) 402 { 403 int i, j, k, m; 404 u8 *p_8; 405 u32 *p_32; 406 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 407 generic_spd_eeprom_t 408 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 409 410 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 411 fsl_ddr_get_spd(spd[i], i); 412 413 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 414 puts("Byte (hex) "); 415 k = 1; 416 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 417 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 418 printf("Dimm%d ", k++); 419 } 420 puts("\n"); 421 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 422 m = 0; 423 printf("%3d (0x%02x) ", k, k); 424 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 425 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 426 p_8 = (u8 *) &spd[i][j]; 427 if (p_8[k]) { 428 printf("0x%02x ", p_8[k]); 429 m++; 430 } else 431 puts(" "); 432 } 433 } 434 if (m) 435 puts("\n"); 436 else 437 puts("\r"); 438 } 439 440 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 441 switch (i) { 442 case 0: 443 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 444 break; 445 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 446 case 1: 447 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 448 break; 449 #endif 450 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 451 case 2: 452 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; 453 break; 454 #endif 455 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 456 case 3: 457 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR; 458 break; 459 #endif 460 default: 461 printf("%s unexpected controller number = %u\n", 462 __func__, i); 463 return; 464 } 465 } 466 printf("DDR registers dump for all controllers " 467 "(zero vaule is omitted)...\n"); 468 puts("Offset (hex) "); 469 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 470 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 471 puts("\n"); 472 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 473 m = 0; 474 printf("%6d (0x%04x)", k * 4, k * 4); 475 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 476 p_32 = (u32 *) ddr[i]; 477 if (p_32[k]) { 478 printf(" 0x%08x", p_32[k]); 479 m++; 480 } else 481 puts(" "); 482 } 483 if (m) 484 puts("\n"); 485 else 486 puts("\r"); 487 } 488 puts("\n"); 489 } 490 491 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 492 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 493 { 494 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 495 unsigned long epn; 496 u32 tsize, valid, ptr; 497 int ddr_esel; 498 499 clear_ddr_tlbs_phys(p_addr, size>>20); 500 501 /* Setup new tlb to cover the physical address */ 502 setup_ddr_tlbs_phys(p_addr, size>>20); 503 504 ptr = vstart; 505 ddr_esel = find_tlb_idx((void *)ptr, 1); 506 if (ddr_esel != -1) { 507 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 508 } else { 509 printf("TLB error in function %s\n", __func__); 510 return -1; 511 } 512 513 return 0; 514 } 515 516 /* 517 * slide the testing window up to test another area 518 * for 32_bit system, the maximum testable memory is limited to 519 * CONFIG_MAX_MEM_MAPPED 520 */ 521 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 522 { 523 phys_addr_t test_cap, p_addr; 524 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 525 526 #if !defined(CONFIG_PHYS_64BIT) || \ 527 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 528 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 529 test_cap = p_size; 530 #else 531 test_cap = gd->ram_size; 532 #endif 533 p_addr = (*vstart) + (*size) + (*phys_offset); 534 if (p_addr < test_cap - 1) { 535 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 536 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 537 return -1; 538 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 539 *size = (u32) p_size; 540 printf("Testing 0x%08llx - 0x%08llx\n", 541 (u64)(*vstart) + (*phys_offset), 542 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 543 } else 544 return 1; 545 546 return 0; 547 } 548 549 /* initialization for testing area */ 550 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 551 { 552 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 553 554 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 555 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 556 *phys_offset = 0; 557 558 #if !defined(CONFIG_PHYS_64BIT) || \ 559 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 560 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 561 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 562 puts("Cannot test more than "); 563 print_size(CONFIG_MAX_MEM_MAPPED, 564 " without proper 36BIT support.\n"); 565 } 566 #endif 567 printf("Testing 0x%08llx - 0x%08llx\n", 568 (u64)(*vstart) + (*phys_offset), 569 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 570 571 return 0; 572 } 573 574 /* invalid TLBs for DDR and remap as normal after testing */ 575 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 576 { 577 unsigned long epn; 578 u32 tsize, valid, ptr; 579 phys_addr_t rpn = 0; 580 int ddr_esel; 581 582 /* disable the TLBs for this testing */ 583 ptr = *vstart; 584 585 while (ptr < (*vstart) + (*size)) { 586 ddr_esel = find_tlb_idx((void *)ptr, 1); 587 if (ddr_esel != -1) { 588 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 589 disable_tlb(ddr_esel); 590 } 591 ptr += TSIZE_TO_BYTES(tsize); 592 } 593 594 puts("Remap DDR "); 595 setup_ddr_tlbs(gd->ram_size>>20); 596 puts("\n"); 597 598 return 0; 599 } 600 601 void arch_memory_failure_handle(void) 602 { 603 dump_spd_ddr_reg(); 604 } 605 #endif 606