1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_ifc.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_lbc.h> 39 #include <post.h> 40 #include <asm/processor.h> 41 #include <asm/fsl_ddr_sdram.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 /* 46 * Default board reset function 47 */ 48 static void 49 __board_reset(void) 50 { 51 /* Do nothing */ 52 } 53 void board_reset(void) __attribute__((weak, alias("__board_reset"))); 54 55 int checkcpu (void) 56 { 57 sys_info_t sysinfo; 58 uint pvr, svr; 59 uint ver; 60 uint major, minor; 61 struct cpu_type *cpu; 62 char buf1[32], buf2[32]; 63 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 64 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 65 #endif /* CONFIG_FSL_CORENET */ 66 #ifdef CONFIG_DDR_CLK_FREQ 67 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 68 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 69 #else 70 #ifdef CONFIG_FSL_CORENET 71 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 72 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 73 #else 74 u32 ddr_ratio = 0; 75 #endif /* CONFIG_FSL_CORENET */ 76 #endif /* CONFIG_DDR_CLK_FREQ */ 77 unsigned int i, core, nr_cores = cpu_numcores(); 78 u32 mask = cpu_mask(); 79 80 svr = get_svr(); 81 major = SVR_MAJ(svr); 82 minor = SVR_MIN(svr); 83 84 if (cpu_numcores() > 1) { 85 #ifndef CONFIG_MP 86 puts("Unicore software on multiprocessor system!!\n" 87 "To enable mutlticore build define CONFIG_MP\n"); 88 #endif 89 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 90 printf("CPU%d: ", pic->whoami); 91 } else { 92 puts("CPU: "); 93 } 94 95 cpu = gd->cpu; 96 97 puts(cpu->name); 98 if (IS_E_PROCESSOR(svr)) 99 puts("E"); 100 101 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 102 103 pvr = get_pvr(); 104 ver = PVR_VER(pvr); 105 major = PVR_MAJ(pvr); 106 minor = PVR_MIN(pvr); 107 108 printf("Core: "); 109 switch(ver) { 110 case PVR_VER_E500_V1: 111 case PVR_VER_E500_V2: 112 puts("E500"); 113 break; 114 case PVR_VER_E500MC: 115 puts("E500MC"); 116 break; 117 case PVR_VER_E5500: 118 puts("E5500"); 119 break; 120 case PVR_VER_E6500: 121 puts("E6500"); 122 break; 123 default: 124 puts("Unknown"); 125 break; 126 } 127 128 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 129 130 get_sys_info(&sysinfo); 131 132 puts("Clock Configuration:"); 133 for_each_cpu(i, core, nr_cores, mask) { 134 if (!(i & 3)) 135 printf ("\n "); 136 printf("CPU%d:%-4s MHz, ", core, 137 strmhz(buf1, sysinfo.freqProcessor[core])); 138 } 139 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 140 141 #ifdef CONFIG_FSL_CORENET 142 if (ddr_sync == 1) { 143 printf(" DDR:%-4s MHz (%s MT/s data rate) " 144 "(Synchronous), ", 145 strmhz(buf1, sysinfo.freqDDRBus/2), 146 strmhz(buf2, sysinfo.freqDDRBus)); 147 } else { 148 printf(" DDR:%-4s MHz (%s MT/s data rate) " 149 "(Asynchronous), ", 150 strmhz(buf1, sysinfo.freqDDRBus/2), 151 strmhz(buf2, sysinfo.freqDDRBus)); 152 } 153 #else 154 switch (ddr_ratio) { 155 case 0x0: 156 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 157 strmhz(buf1, sysinfo.freqDDRBus/2), 158 strmhz(buf2, sysinfo.freqDDRBus)); 159 break; 160 case 0x7: 161 printf(" DDR:%-4s MHz (%s MT/s data rate) " 162 "(Synchronous), ", 163 strmhz(buf1, sysinfo.freqDDRBus/2), 164 strmhz(buf2, sysinfo.freqDDRBus)); 165 break; 166 default: 167 printf(" DDR:%-4s MHz (%s MT/s data rate) " 168 "(Asynchronous), ", 169 strmhz(buf1, sysinfo.freqDDRBus/2), 170 strmhz(buf2, sysinfo.freqDDRBus)); 171 break; 172 } 173 #endif 174 175 #if defined(CONFIG_FSL_LBC) 176 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 177 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 178 } else { 179 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 180 sysinfo.freqLocalBus); 181 } 182 #endif 183 184 #if defined(CONFIG_FSL_IFC) 185 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 186 #endif 187 188 #ifdef CONFIG_CPM2 189 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 190 #endif 191 192 #ifdef CONFIG_QE 193 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 194 #endif 195 196 #ifdef CONFIG_SYS_DPAA_FMAN 197 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 198 printf(" FMAN%d: %s MHz\n", i + 1, 199 strmhz(buf1, sysinfo.freqFMan[i])); 200 } 201 #endif 202 203 #ifdef CONFIG_SYS_DPAA_PME 204 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 205 #endif 206 207 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 208 209 return 0; 210 } 211 212 213 /* ------------------------------------------------------------------------- */ 214 215 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 216 { 217 /* Everything after the first generation of PQ3 parts has RSTCR */ 218 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 219 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 220 unsigned long val, msr; 221 222 /* 223 * Initiate hard reset in debug control register DBCR0 224 * Make sure MSR[DE] = 1. This only resets the core. 225 */ 226 msr = mfmsr (); 227 msr |= MSR_DE; 228 mtmsr (msr); 229 230 val = mfspr(DBCR0); 231 val |= 0x70000000; 232 mtspr(DBCR0,val); 233 #else 234 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 235 236 /* Attempt board-specific reset */ 237 board_reset(); 238 239 /* Next try asserting HRESET_REQ */ 240 out_be32(&gur->rstcr, 0x2); 241 udelay(100); 242 #endif 243 244 return 1; 245 } 246 247 248 /* 249 * Get timebase clock frequency 250 */ 251 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 252 #define CONFIG_SYS_FSL_TBCLK_DIV 8 253 #endif 254 unsigned long get_tbclk (void) 255 { 256 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 257 258 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 259 } 260 261 262 #if defined(CONFIG_WATCHDOG) 263 void 264 watchdog_reset(void) 265 { 266 int re_enable = disable_interrupts(); 267 reset_85xx_watchdog(); 268 if (re_enable) enable_interrupts(); 269 } 270 271 void 272 reset_85xx_watchdog(void) 273 { 274 /* 275 * Clear TSR(WIS) bit by writing 1 276 */ 277 mtspr(SPRN_TSR, TSR_WIS); 278 } 279 #endif /* CONFIG_WATCHDOG */ 280 281 /* 282 * Initializes on-chip MMC controllers. 283 * to override, implement board_mmc_init() 284 */ 285 int cpu_mmc_init(bd_t *bis) 286 { 287 #ifdef CONFIG_FSL_ESDHC 288 return fsl_esdhc_mmc_init(bis); 289 #else 290 return 0; 291 #endif 292 } 293 294 /* 295 * Print out the state of various machine registers. 296 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 297 * parameters for IFC and TLBs 298 */ 299 void mpc85xx_reginfo(void) 300 { 301 print_tlbcam(); 302 print_laws(); 303 #if defined(CONFIG_FSL_LBC) 304 print_lbc_regs(); 305 #endif 306 #ifdef CONFIG_FSL_IFC 307 print_ifc_regs(); 308 #endif 309 310 } 311 312 /* Common ddr init for non-corenet fsl 85xx platforms */ 313 #ifndef CONFIG_FSL_CORENET 314 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) 315 phys_size_t initdram(int board_type) 316 { 317 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 318 return fsl_ddr_sdram_size(); 319 #else 320 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 321 #endif 322 } 323 #else /* CONFIG_SYS_RAMBOOT */ 324 phys_size_t initdram(int board_type) 325 { 326 phys_size_t dram_size = 0; 327 328 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 329 { 330 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 331 unsigned int x = 10; 332 unsigned int i; 333 334 /* 335 * Work around to stabilize DDR DLL 336 */ 337 out_be32(&gur->ddrdllcr, 0x81000000); 338 asm("sync;isync;msync"); 339 udelay(200); 340 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 341 setbits_be32(&gur->devdisr, 0x00010000); 342 for (i = 0; i < x; i++) 343 ; 344 clrbits_be32(&gur->devdisr, 0x00010000); 345 x++; 346 } 347 } 348 #endif 349 350 #if defined(CONFIG_SPD_EEPROM) || \ 351 defined(CONFIG_DDR_SPD) || \ 352 defined(CONFIG_SYS_DDR_RAW_TIMING) 353 dram_size = fsl_ddr_sdram(); 354 #else 355 dram_size = fixed_sdram(); 356 #endif 357 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 358 dram_size *= 0x100000; 359 360 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 361 /* 362 * Initialize and enable DDR ECC. 363 */ 364 ddr_enable_ecc(dram_size); 365 #endif 366 367 #if defined(CONFIG_FSL_LBC) 368 /* Some boards also have sdram on the lbc */ 369 lbc_sdram_init(); 370 #endif 371 372 debug("DDR: "); 373 return dram_size; 374 } 375 #endif /* CONFIG_SYS_RAMBOOT */ 376 #endif 377 378 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 379 380 /* Board-specific functions defined in each board's ddr.c */ 381 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 382 unsigned int ctrl_num); 383 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 384 phys_addr_t *rpn); 385 unsigned int 386 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 387 388 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 389 390 static void dump_spd_ddr_reg(void) 391 { 392 int i, j, k, m; 393 u8 *p_8; 394 u32 *p_32; 395 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 396 generic_spd_eeprom_t 397 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 398 399 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 400 fsl_ddr_get_spd(spd[i], i); 401 402 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 403 puts("Byte (hex) "); 404 k = 1; 405 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 406 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 407 printf("Dimm%d ", k++); 408 } 409 puts("\n"); 410 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 411 m = 0; 412 printf("%3d (0x%02x) ", k, k); 413 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 414 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 415 p_8 = (u8 *) &spd[i][j]; 416 if (p_8[k]) { 417 printf("0x%02x ", p_8[k]); 418 m++; 419 } else 420 puts(" "); 421 } 422 } 423 if (m) 424 puts("\n"); 425 else 426 puts("\r"); 427 } 428 429 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 430 switch (i) { 431 case 0: 432 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 433 break; 434 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 435 case 1: 436 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 437 break; 438 #endif 439 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 440 case 2: 441 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; 442 break; 443 #endif 444 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 445 case 3: 446 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR; 447 break; 448 #endif 449 default: 450 printf("%s unexpected controller number = %u\n", 451 __func__, i); 452 return; 453 } 454 } 455 printf("DDR registers dump for all controllers " 456 "(zero vaule is omitted)...\n"); 457 puts("Offset (hex) "); 458 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 459 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 460 puts("\n"); 461 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 462 m = 0; 463 printf("%6d (0x%04x)", k * 4, k * 4); 464 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 465 p_32 = (u32 *) ddr[i]; 466 if (p_32[k]) { 467 printf(" 0x%08x", p_32[k]); 468 m++; 469 } else 470 puts(" "); 471 } 472 if (m) 473 puts("\n"); 474 else 475 puts("\r"); 476 } 477 puts("\n"); 478 } 479 480 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 481 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 482 { 483 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 484 unsigned long epn; 485 u32 tsize, valid, ptr; 486 int ddr_esel; 487 488 clear_ddr_tlbs_phys(p_addr, size>>20); 489 490 /* Setup new tlb to cover the physical address */ 491 setup_ddr_tlbs_phys(p_addr, size>>20); 492 493 ptr = vstart; 494 ddr_esel = find_tlb_idx((void *)ptr, 1); 495 if (ddr_esel != -1) { 496 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 497 } else { 498 printf("TLB error in function %s\n", __func__); 499 return -1; 500 } 501 502 return 0; 503 } 504 505 /* 506 * slide the testing window up to test another area 507 * for 32_bit system, the maximum testable memory is limited to 508 * CONFIG_MAX_MEM_MAPPED 509 */ 510 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 511 { 512 phys_addr_t test_cap, p_addr; 513 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 514 515 #if !defined(CONFIG_PHYS_64BIT) || \ 516 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 517 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 518 test_cap = p_size; 519 #else 520 test_cap = gd->ram_size; 521 #endif 522 p_addr = (*vstart) + (*size) + (*phys_offset); 523 if (p_addr < test_cap - 1) { 524 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 525 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 526 return -1; 527 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 528 *size = (u32) p_size; 529 printf("Testing 0x%08llx - 0x%08llx\n", 530 (u64)(*vstart) + (*phys_offset), 531 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 532 } else 533 return 1; 534 535 return 0; 536 } 537 538 /* initialization for testing area */ 539 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 540 { 541 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 542 543 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 544 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 545 *phys_offset = 0; 546 547 #if !defined(CONFIG_PHYS_64BIT) || \ 548 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 549 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 550 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 551 puts("Cannot test more than "); 552 print_size(CONFIG_MAX_MEM_MAPPED, 553 " without proper 36BIT support.\n"); 554 } 555 #endif 556 printf("Testing 0x%08llx - 0x%08llx\n", 557 (u64)(*vstart) + (*phys_offset), 558 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 559 560 return 0; 561 } 562 563 /* invalid TLBs for DDR and remap as normal after testing */ 564 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 565 { 566 unsigned long epn; 567 u32 tsize, valid, ptr; 568 phys_addr_t rpn = 0; 569 int ddr_esel; 570 571 /* disable the TLBs for this testing */ 572 ptr = *vstart; 573 574 while (ptr < (*vstart) + (*size)) { 575 ddr_esel = find_tlb_idx((void *)ptr, 1); 576 if (ddr_esel != -1) { 577 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 578 disable_tlb(ddr_esel); 579 } 580 ptr += TSIZE_TO_BYTES(tsize); 581 } 582 583 puts("Remap DDR "); 584 setup_ddr_tlbs(gd->ram_size>>20); 585 puts("\n"); 586 587 return 0; 588 } 589 590 void arch_memory_failure_handle(void) 591 { 592 dump_spd_ddr_reg(); 593 } 594 #endif 595