xref: /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/Makefile (revision 5ba40eec72a1e45a262c4c8a6aa20760e61fb7ec) 
1#
2# (C) Copyright 2006
3# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4#
5# (C) Copyright 2002,2003 Motorola Inc.
6# Xianghua Xiao,X.Xiao@motorola.com
7#
8# See file CREDITS for list of people who contributed to this
9# project.
10#
11# This program is free software; you can redistribute it and/or
12# modify it under the terms of the GNU General Public License as
13# published by the Free Software Foundation; either version 2 of
14# the License, or (at your option) any later version.
15#
16# This program is distributed in the hope that it will be useful,
17# but WITHOUT ANY WARRANTY; without even the implied warranty of
18# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19# GNU General Public License for more details.
20#
21# You should have received a copy of the GNU General Public License
22# along with this program; if not, write to the Free Software
23# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24# MA 02111-1307 USA
25#
26
27include $(TOPDIR)/config.mk
28
29LIB	= $(obj)lib$(CPU).o
30
31START	= start.o resetvec.o
32SOBJS-$(CONFIG_MP)	+= release.o
33SOBJS	= $(SOBJS-y)
34
35COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o
36COBJS-$(CONFIG_CPM2)	+= commproc.o
37
38# supports ddr1
39COBJS-$(CONFIG_MPC8540) += ddr-gen1.o
40COBJS-$(CONFIG_MPC8560) += ddr-gen1.o
41COBJS-$(CONFIG_MPC8541) += ddr-gen1.o
42COBJS-$(CONFIG_MPC8555) += ddr-gen1.o
43
44# supports ddr1/2
45COBJS-$(CONFIG_MPC8548) += ddr-gen2.o
46COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
47COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
48
49# supports ddr1/2/3
50COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
51COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
52COBJS-$(CONFIG_MPC8569)	+= ddr-gen3.o
53COBJS-$(CONFIG_P1011)	+= ddr-gen3.o
54COBJS-$(CONFIG_P1012)	+= ddr-gen3.o
55COBJS-$(CONFIG_P1013)	+= ddr-gen3.o
56COBJS-$(CONFIG_P1020)	+= ddr-gen3.o
57COBJS-$(CONFIG_P1021)	+= ddr-gen3.o
58COBJS-$(CONFIG_P1022)	+= ddr-gen3.o
59COBJS-$(CONFIG_P2010)	+= ddr-gen3.o
60COBJS-$(CONFIG_P2020)	+= ddr-gen3.o
61COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
62COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
63COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
64
65COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
66COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
67COBJS-$(CONFIG_FSL_CORENET) += liodn.o
68COBJS-$(CONFIG_MP)	+= mp.o
69COBJS-$(CONFIG_PCI)	+= pci.o
70COBJS-$(CONFIG_FSL_CORENET) += portals.o
71
72# various SoC specific assignments
73COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
74
75COBJS-$(CONFIG_QE)	+= qe_io.o
76COBJS-$(CONFIG_CPM2)	+= serial_scc.o
77COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o
78
79# SoC specific SERDES support
80COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
81COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
82COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o
83COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
84COBJS-$(CONFIG_P1013)	+= p1013_serdes.o
85COBJS-$(CONFIG_P1022)	+= p1022_serdes.o
86COBJS-$(CONFIG_P2010)	+= p2020_serdes.o
87COBJS-$(CONFIG_P2020)	+= p2020_serdes.o
88COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
89
90COBJS	= $(COBJS-y)
91COBJS	+= cpu.o
92COBJS	+= cpu_init.o
93COBJS	+= cpu_init_early.o
94COBJS	+= interrupts.o
95COBJS	+= speed.o
96COBJS	+= tlb.o
97COBJS	+= traps.o
98
99SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
100OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
101START	:= $(addprefix $(obj),$(START))
102
103all:	$(obj).depend $(START) $(LIB)
104
105$(LIB):	$(OBJS)
106	$(call cmd_link_o_target, $(OBJS))
107
108#########################################################################
109
110# defines $(obj).depend target
111include $(SRCTREE)/rules.mk
112
113sinclude $(obj).depend
114
115#########################################################################
116