1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_SBC8548 12 bool "Support sbc8548" 13 select ARCH_MPC8548 14 15config TARGET_SOCRATES 16 bool "Support socrates" 17 select ARCH_MPC8544 18 19config TARGET_B4420QDS 20 bool "Support B4420QDS" 21 select ARCH_B4420 22 select SUPPORT_SPL 23 select PHYS_64BIT 24 25config TARGET_B4860QDS 26 bool "Support B4860QDS" 27 select ARCH_B4860 28 select BOARD_LATE_INIT if CHAIN_OF_TRUST 29 select SUPPORT_SPL 30 select PHYS_64BIT 31 32config TARGET_BSC9131RDB 33 bool "Support BSC9131RDB" 34 select ARCH_BSC9131 35 select SUPPORT_SPL 36 select BOARD_EARLY_INIT_F 37 38config TARGET_BSC9132QDS 39 bool "Support BSC9132QDS" 40 select ARCH_BSC9132 41 select BOARD_LATE_INIT if CHAIN_OF_TRUST 42 select SUPPORT_SPL 43 select BOARD_EARLY_INIT_F 44 45config TARGET_C29XPCIE 46 bool "Support C29XPCIE" 47 select ARCH_C29X 48 select BOARD_LATE_INIT if CHAIN_OF_TRUST 49 select SUPPORT_SPL 50 select SUPPORT_TPL 51 select PHYS_64BIT 52 53config TARGET_P3041DS 54 bool "Support P3041DS" 55 select PHYS_64BIT 56 select ARCH_P3041 57 select BOARD_LATE_INIT if CHAIN_OF_TRUST 58 59config TARGET_P4080DS 60 bool "Support P4080DS" 61 select PHYS_64BIT 62 select ARCH_P4080 63 select BOARD_LATE_INIT if CHAIN_OF_TRUST 64 65config TARGET_P5020DS 66 bool "Support P5020DS" 67 select PHYS_64BIT 68 select ARCH_P5020 69 select BOARD_LATE_INIT if CHAIN_OF_TRUST 70 71config TARGET_P5040DS 72 bool "Support P5040DS" 73 select PHYS_64BIT 74 select ARCH_P5040 75 select BOARD_LATE_INIT if CHAIN_OF_TRUST 76 77config TARGET_MPC8536DS 78 bool "Support MPC8536DS" 79 select ARCH_MPC8536 80# Use DDR3 controller with DDR2 DIMMs on this board 81 select SYS_FSL_DDRC_GEN3 82 83config TARGET_MPC8540ADS 84 bool "Support MPC8540ADS" 85 select ARCH_MPC8540 86 87config TARGET_MPC8541CDS 88 bool "Support MPC8541CDS" 89 select ARCH_MPC8541 90 91config TARGET_MPC8544DS 92 bool "Support MPC8544DS" 93 select ARCH_MPC8544 94 95config TARGET_MPC8548CDS 96 bool "Support MPC8548CDS" 97 select ARCH_MPC8548 98 99config TARGET_MPC8555CDS 100 bool "Support MPC8555CDS" 101 select ARCH_MPC8555 102 103config TARGET_MPC8560ADS 104 bool "Support MPC8560ADS" 105 select ARCH_MPC8560 106 107config TARGET_MPC8568MDS 108 bool "Support MPC8568MDS" 109 select ARCH_MPC8568 110 111config TARGET_MPC8569MDS 112 bool "Support MPC8569MDS" 113 select ARCH_MPC8569 114 115config TARGET_MPC8572DS 116 bool "Support MPC8572DS" 117 select ARCH_MPC8572 118# Use DDR3 controller with DDR2 DIMMs on this board 119 select SYS_FSL_DDRC_GEN3 120 121config TARGET_P1010RDB_PA 122 bool "Support P1010RDB_PA" 123 select ARCH_P1010 124 select BOARD_LATE_INIT if CHAIN_OF_TRUST 125 select SUPPORT_SPL 126 select SUPPORT_TPL 127 128config TARGET_P1010RDB_PB 129 bool "Support P1010RDB_PB" 130 select ARCH_P1010 131 select BOARD_LATE_INIT if CHAIN_OF_TRUST 132 select SUPPORT_SPL 133 select SUPPORT_TPL 134 135config TARGET_P1022DS 136 bool "Support P1022DS" 137 select ARCH_P1022 138 select SUPPORT_SPL 139 select SUPPORT_TPL 140 141config TARGET_P1023RDB 142 bool "Support P1023RDB" 143 select ARCH_P1023 144 145config TARGET_P1020MBG 146 bool "Support P1020MBG-PC" 147 select SUPPORT_SPL 148 select SUPPORT_TPL 149 select ARCH_P1020 150 151config TARGET_P1020RDB_PC 152 bool "Support P1020RDB-PC" 153 select SUPPORT_SPL 154 select SUPPORT_TPL 155 select ARCH_P1020 156 157config TARGET_P1020RDB_PD 158 bool "Support P1020RDB-PD" 159 select SUPPORT_SPL 160 select SUPPORT_TPL 161 select ARCH_P1020 162 163config TARGET_P1020UTM 164 bool "Support P1020UTM" 165 select SUPPORT_SPL 166 select SUPPORT_TPL 167 select ARCH_P1020 168 169config TARGET_P1021RDB 170 bool "Support P1021RDB" 171 select SUPPORT_SPL 172 select SUPPORT_TPL 173 select ARCH_P1021 174 175config TARGET_P1024RDB 176 bool "Support P1024RDB" 177 select SUPPORT_SPL 178 select SUPPORT_TPL 179 select ARCH_P1024 180 181config TARGET_P1025RDB 182 bool "Support P1025RDB" 183 select SUPPORT_SPL 184 select SUPPORT_TPL 185 select ARCH_P1025 186 187config TARGET_P2020RDB 188 bool "Support P2020RDB-PC" 189 select SUPPORT_SPL 190 select SUPPORT_TPL 191 select ARCH_P2020 192 193config TARGET_P1_TWR 194 bool "Support p1_twr" 195 select ARCH_P1025 196 197config TARGET_P2041RDB 198 bool "Support P2041RDB" 199 select ARCH_P2041 200 select BOARD_LATE_INIT if CHAIN_OF_TRUST 201 select PHYS_64BIT 202 203config TARGET_QEMU_PPCE500 204 bool "Support qemu-ppce500" 205 select ARCH_QEMU_E500 206 select PHYS_64BIT 207 208config TARGET_T1024QDS 209 bool "Support T1024QDS" 210 select ARCH_T1024 211 select BOARD_LATE_INIT if CHAIN_OF_TRUST 212 select SUPPORT_SPL 213 select PHYS_64BIT 214 215config TARGET_T1023RDB 216 bool "Support T1023RDB" 217 select ARCH_T1023 218 select BOARD_LATE_INIT if CHAIN_OF_TRUST 219 select SUPPORT_SPL 220 select PHYS_64BIT 221 222config TARGET_T1024RDB 223 bool "Support T1024RDB" 224 select ARCH_T1024 225 select BOARD_LATE_INIT if CHAIN_OF_TRUST 226 select SUPPORT_SPL 227 select PHYS_64BIT 228 229config TARGET_T1040QDS 230 bool "Support T1040QDS" 231 select ARCH_T1040 232 select BOARD_LATE_INIT if CHAIN_OF_TRUST 233 select PHYS_64BIT 234 235config TARGET_T1040RDB 236 bool "Support T1040RDB" 237 select ARCH_T1040 238 select BOARD_LATE_INIT if CHAIN_OF_TRUST 239 select SUPPORT_SPL 240 select PHYS_64BIT 241 242config TARGET_T1040D4RDB 243 bool "Support T1040D4RDB" 244 select ARCH_T1040 245 select BOARD_LATE_INIT if CHAIN_OF_TRUST 246 select SUPPORT_SPL 247 select PHYS_64BIT 248 249config TARGET_T1042RDB 250 bool "Support T1042RDB" 251 select ARCH_T1042 252 select BOARD_LATE_INIT if CHAIN_OF_TRUST 253 select SUPPORT_SPL 254 select PHYS_64BIT 255 256config TARGET_T1042D4RDB 257 bool "Support T1042D4RDB" 258 select ARCH_T1042 259 select BOARD_LATE_INIT if CHAIN_OF_TRUST 260 select SUPPORT_SPL 261 select PHYS_64BIT 262 263config TARGET_T1042RDB_PI 264 bool "Support T1042RDB_PI" 265 select ARCH_T1042 266 select BOARD_LATE_INIT if CHAIN_OF_TRUST 267 select SUPPORT_SPL 268 select PHYS_64BIT 269 270config TARGET_T2080QDS 271 bool "Support T2080QDS" 272 select ARCH_T2080 273 select BOARD_LATE_INIT if CHAIN_OF_TRUST 274 select SUPPORT_SPL 275 select PHYS_64BIT 276 277config TARGET_T2080RDB 278 bool "Support T2080RDB" 279 select ARCH_T2080 280 select BOARD_LATE_INIT if CHAIN_OF_TRUST 281 select SUPPORT_SPL 282 select PHYS_64BIT 283 284config TARGET_T2081QDS 285 bool "Support T2081QDS" 286 select ARCH_T2081 287 select SUPPORT_SPL 288 select PHYS_64BIT 289 290config TARGET_T4160QDS 291 bool "Support T4160QDS" 292 select ARCH_T4160 293 select BOARD_LATE_INIT if CHAIN_OF_TRUST 294 select SUPPORT_SPL 295 select PHYS_64BIT 296 297config TARGET_T4160RDB 298 bool "Support T4160RDB" 299 select ARCH_T4160 300 select SUPPORT_SPL 301 select PHYS_64BIT 302 303config TARGET_T4240QDS 304 bool "Support T4240QDS" 305 select ARCH_T4240 306 select BOARD_LATE_INIT if CHAIN_OF_TRUST 307 select SUPPORT_SPL 308 select PHYS_64BIT 309 310config TARGET_T4240RDB 311 bool "Support T4240RDB" 312 select ARCH_T4240 313 select SUPPORT_SPL 314 select PHYS_64BIT 315 316config TARGET_CONTROLCENTERD 317 bool "Support controlcenterd" 318 select ARCH_P1022 319 320config TARGET_KMP204X 321 bool "Support kmp204x" 322 select ARCH_P2041 323 select PHYS_64BIT 324 325config TARGET_XPEDITE520X 326 bool "Support xpedite520x" 327 select ARCH_MPC8548 328 329config TARGET_XPEDITE537X 330 bool "Support xpedite537x" 331 select ARCH_MPC8572 332# Use DDR3 controller with DDR2 DIMMs on this board 333 select SYS_FSL_DDRC_GEN3 334 335config TARGET_XPEDITE550X 336 bool "Support xpedite550x" 337 select ARCH_P2020 338 339config TARGET_UCP1020 340 bool "Support uCP1020" 341 select ARCH_P1020 342 343config TARGET_CYRUS_P5020 344 bool "Support Varisys Cyrus P5020" 345 select ARCH_P5020 346 select PHYS_64BIT 347 348config TARGET_CYRUS_P5040 349 bool "Support Varisys Cyrus P5040" 350 select ARCH_P5040 351 select PHYS_64BIT 352 353endchoice 354 355config ARCH_B4420 356 bool 357 select E500MC 358 select E6500 359 select FSL_LAW 360 select SYS_FSL_DDR_VER_47 361 select SYS_FSL_ERRATUM_A004477 362 select SYS_FSL_ERRATUM_A005871 363 select SYS_FSL_ERRATUM_A006379 364 select SYS_FSL_ERRATUM_A006384 365 select SYS_FSL_ERRATUM_A006475 366 select SYS_FSL_ERRATUM_A006593 367 select SYS_FSL_ERRATUM_A007075 368 select SYS_FSL_ERRATUM_A007186 369 select SYS_FSL_ERRATUM_A007212 370 select SYS_FSL_ERRATUM_A009942 371 select SYS_FSL_HAS_DDR3 372 select SYS_FSL_HAS_SEC 373 select SYS_FSL_QORIQ_CHASSIS2 374 select SYS_FSL_SEC_BE 375 select SYS_FSL_SEC_COMPAT_4 376 select SYS_PPC64 377 select FSL_IFC 378 379config ARCH_B4860 380 bool 381 select E500MC 382 select E6500 383 select FSL_LAW 384 select SYS_FSL_DDR_VER_47 385 select SYS_FSL_ERRATUM_A004477 386 select SYS_FSL_ERRATUM_A005871 387 select SYS_FSL_ERRATUM_A006379 388 select SYS_FSL_ERRATUM_A006384 389 select SYS_FSL_ERRATUM_A006475 390 select SYS_FSL_ERRATUM_A006593 391 select SYS_FSL_ERRATUM_A007075 392 select SYS_FSL_ERRATUM_A007186 393 select SYS_FSL_ERRATUM_A007212 394 select SYS_FSL_ERRATUM_A007907 395 select SYS_FSL_ERRATUM_A009942 396 select SYS_FSL_HAS_DDR3 397 select SYS_FSL_HAS_SEC 398 select SYS_FSL_QORIQ_CHASSIS2 399 select SYS_FSL_SEC_BE 400 select SYS_FSL_SEC_COMPAT_4 401 select SYS_PPC64 402 select FSL_IFC 403 404config ARCH_BSC9131 405 bool 406 select FSL_LAW 407 select SYS_FSL_DDR_VER_44 408 select SYS_FSL_ERRATUM_A004477 409 select SYS_FSL_ERRATUM_A005125 410 select SYS_FSL_ERRATUM_ESDHC111 411 select SYS_FSL_HAS_DDR3 412 select SYS_FSL_HAS_SEC 413 select SYS_FSL_SEC_BE 414 select SYS_FSL_SEC_COMPAT_4 415 select FSL_IFC 416 417config ARCH_BSC9132 418 bool 419 select FSL_LAW 420 select SYS_FSL_DDR_VER_46 421 select SYS_FSL_ERRATUM_A004477 422 select SYS_FSL_ERRATUM_A005125 423 select SYS_FSL_ERRATUM_A005434 424 select SYS_FSL_ERRATUM_ESDHC111 425 select SYS_FSL_ERRATUM_I2C_A004447 426 select SYS_FSL_ERRATUM_IFC_A002769 427 select SYS_FSL_HAS_DDR3 428 select SYS_FSL_HAS_SEC 429 select SYS_FSL_SEC_BE 430 select SYS_FSL_SEC_COMPAT_4 431 select SYS_PPC_E500_USE_DEBUG_TLB 432 select FSL_IFC 433 434config ARCH_C29X 435 bool 436 select FSL_LAW 437 select SYS_FSL_DDR_VER_46 438 select SYS_FSL_ERRATUM_A005125 439 select SYS_FSL_ERRATUM_ESDHC111 440 select SYS_FSL_HAS_DDR3 441 select SYS_FSL_HAS_SEC 442 select SYS_FSL_SEC_BE 443 select SYS_FSL_SEC_COMPAT_6 444 select SYS_PPC_E500_USE_DEBUG_TLB 445 select FSL_IFC 446 447config ARCH_MPC8536 448 bool 449 select FSL_LAW 450 select SYS_FSL_ERRATUM_A004508 451 select SYS_FSL_ERRATUM_A005125 452 select SYS_FSL_HAS_DDR2 453 select SYS_FSL_HAS_DDR3 454 select SYS_FSL_HAS_SEC 455 select SYS_FSL_SEC_BE 456 select SYS_FSL_SEC_COMPAT_2 457 select SYS_PPC_E500_USE_DEBUG_TLB 458 459config ARCH_MPC8540 460 bool 461 select FSL_LAW 462 select SYS_FSL_HAS_DDR1 463 464config ARCH_MPC8541 465 bool 466 select FSL_LAW 467 select SYS_FSL_HAS_DDR1 468 select SYS_FSL_HAS_SEC 469 select SYS_FSL_SEC_BE 470 select SYS_FSL_SEC_COMPAT_2 471 472config ARCH_MPC8544 473 bool 474 select FSL_LAW 475 select SYS_FSL_ERRATUM_A005125 476 select SYS_FSL_HAS_DDR2 477 select SYS_FSL_HAS_SEC 478 select SYS_FSL_SEC_BE 479 select SYS_FSL_SEC_COMPAT_2 480 select SYS_PPC_E500_USE_DEBUG_TLB 481 482config ARCH_MPC8548 483 bool 484 select FSL_LAW 485 select SYS_FSL_ERRATUM_A005125 486 select SYS_FSL_ERRATUM_NMG_DDR120 487 select SYS_FSL_ERRATUM_NMG_LBC103 488 select SYS_FSL_ERRATUM_NMG_ETSEC129 489 select SYS_FSL_ERRATUM_I2C_A004447 490 select SYS_FSL_HAS_DDR2 491 select SYS_FSL_HAS_DDR1 492 select SYS_FSL_HAS_SEC 493 select SYS_FSL_SEC_BE 494 select SYS_FSL_SEC_COMPAT_2 495 select SYS_PPC_E500_USE_DEBUG_TLB 496 497config ARCH_MPC8555 498 bool 499 select FSL_LAW 500 select SYS_FSL_HAS_DDR1 501 select SYS_FSL_HAS_SEC 502 select SYS_FSL_SEC_BE 503 select SYS_FSL_SEC_COMPAT_2 504 505config ARCH_MPC8560 506 bool 507 select FSL_LAW 508 select SYS_FSL_HAS_DDR1 509 510config ARCH_MPC8568 511 bool 512 select FSL_LAW 513 select SYS_FSL_HAS_DDR2 514 select SYS_FSL_HAS_SEC 515 select SYS_FSL_SEC_BE 516 select SYS_FSL_SEC_COMPAT_2 517 518config ARCH_MPC8569 519 bool 520 select FSL_LAW 521 select SYS_FSL_ERRATUM_A004508 522 select SYS_FSL_ERRATUM_A005125 523 select SYS_FSL_HAS_DDR3 524 select SYS_FSL_HAS_SEC 525 select SYS_FSL_SEC_BE 526 select SYS_FSL_SEC_COMPAT_2 527 528config ARCH_MPC8572 529 bool 530 select FSL_LAW 531 select SYS_FSL_ERRATUM_A004508 532 select SYS_FSL_ERRATUM_A005125 533 select SYS_FSL_ERRATUM_DDR_115 534 select SYS_FSL_ERRATUM_DDR111_DDR134 535 select SYS_FSL_HAS_DDR2 536 select SYS_FSL_HAS_DDR3 537 select SYS_FSL_HAS_SEC 538 select SYS_FSL_SEC_BE 539 select SYS_FSL_SEC_COMPAT_2 540 select SYS_PPC_E500_USE_DEBUG_TLB 541 542config ARCH_P1010 543 bool 544 select FSL_LAW 545 select SYS_FSL_ERRATUM_A004477 546 select SYS_FSL_ERRATUM_A004508 547 select SYS_FSL_ERRATUM_A005125 548 select SYS_FSL_ERRATUM_A006261 549 select SYS_FSL_ERRATUM_A007075 550 select SYS_FSL_ERRATUM_ESDHC111 551 select SYS_FSL_ERRATUM_I2C_A004447 552 select SYS_FSL_ERRATUM_IFC_A002769 553 select SYS_FSL_ERRATUM_P1010_A003549 554 select SYS_FSL_ERRATUM_SEC_A003571 555 select SYS_FSL_ERRATUM_IFC_A003399 556 select SYS_FSL_HAS_DDR3 557 select SYS_FSL_HAS_SEC 558 select SYS_FSL_SEC_BE 559 select SYS_FSL_SEC_COMPAT_4 560 select SYS_PPC_E500_USE_DEBUG_TLB 561 select FSL_IFC 562 563config ARCH_P1011 564 bool 565 select FSL_LAW 566 select SYS_FSL_ERRATUM_A004508 567 select SYS_FSL_ERRATUM_A005125 568 select SYS_FSL_ERRATUM_ELBC_A001 569 select SYS_FSL_ERRATUM_ESDHC111 570 select SYS_FSL_HAS_DDR3 571 select SYS_FSL_HAS_SEC 572 select SYS_FSL_SEC_BE 573 select SYS_FSL_SEC_COMPAT_2 574 select SYS_PPC_E500_USE_DEBUG_TLB 575 576config ARCH_P1020 577 bool 578 select FSL_LAW 579 select SYS_FSL_ERRATUM_A004508 580 select SYS_FSL_ERRATUM_A005125 581 select SYS_FSL_ERRATUM_ELBC_A001 582 select SYS_FSL_ERRATUM_ESDHC111 583 select SYS_FSL_HAS_DDR3 584 select SYS_FSL_HAS_SEC 585 select SYS_FSL_SEC_BE 586 select SYS_FSL_SEC_COMPAT_2 587 select SYS_PPC_E500_USE_DEBUG_TLB 588 589config ARCH_P1021 590 bool 591 select FSL_LAW 592 select SYS_FSL_ERRATUM_A004508 593 select SYS_FSL_ERRATUM_A005125 594 select SYS_FSL_ERRATUM_ELBC_A001 595 select SYS_FSL_ERRATUM_ESDHC111 596 select SYS_FSL_HAS_DDR3 597 select SYS_FSL_HAS_SEC 598 select SYS_FSL_SEC_BE 599 select SYS_FSL_SEC_COMPAT_2 600 select SYS_PPC_E500_USE_DEBUG_TLB 601 602config ARCH_P1022 603 bool 604 select FSL_LAW 605 select SYS_FSL_ERRATUM_A004477 606 select SYS_FSL_ERRATUM_A004508 607 select SYS_FSL_ERRATUM_A005125 608 select SYS_FSL_ERRATUM_ELBC_A001 609 select SYS_FSL_ERRATUM_ESDHC111 610 select SYS_FSL_ERRATUM_SATA_A001 611 select SYS_FSL_HAS_DDR3 612 select SYS_FSL_HAS_SEC 613 select SYS_FSL_SEC_BE 614 select SYS_FSL_SEC_COMPAT_2 615 select SYS_PPC_E500_USE_DEBUG_TLB 616 617config ARCH_P1023 618 bool 619 select FSL_LAW 620 select SYS_FSL_ERRATUM_A004508 621 select SYS_FSL_ERRATUM_A005125 622 select SYS_FSL_ERRATUM_I2C_A004447 623 select SYS_FSL_HAS_DDR3 624 select SYS_FSL_HAS_SEC 625 select SYS_FSL_SEC_BE 626 select SYS_FSL_SEC_COMPAT_4 627 628config ARCH_P1024 629 bool 630 select FSL_LAW 631 select SYS_FSL_ERRATUM_A004508 632 select SYS_FSL_ERRATUM_A005125 633 select SYS_FSL_ERRATUM_ELBC_A001 634 select SYS_FSL_ERRATUM_ESDHC111 635 select SYS_FSL_HAS_DDR3 636 select SYS_FSL_HAS_SEC 637 select SYS_FSL_SEC_BE 638 select SYS_FSL_SEC_COMPAT_2 639 select SYS_PPC_E500_USE_DEBUG_TLB 640 641config ARCH_P1025 642 bool 643 select FSL_LAW 644 select SYS_FSL_ERRATUM_A004508 645 select SYS_FSL_ERRATUM_A005125 646 select SYS_FSL_ERRATUM_ELBC_A001 647 select SYS_FSL_ERRATUM_ESDHC111 648 select SYS_FSL_HAS_DDR3 649 select SYS_FSL_HAS_SEC 650 select SYS_FSL_SEC_BE 651 select SYS_FSL_SEC_COMPAT_2 652 select SYS_PPC_E500_USE_DEBUG_TLB 653 654config ARCH_P2020 655 bool 656 select FSL_LAW 657 select SYS_FSL_ERRATUM_A004477 658 select SYS_FSL_ERRATUM_A004508 659 select SYS_FSL_ERRATUM_A005125 660 select SYS_FSL_ERRATUM_ESDHC111 661 select SYS_FSL_ERRATUM_ESDHC_A001 662 select SYS_FSL_HAS_DDR3 663 select SYS_FSL_HAS_SEC 664 select SYS_FSL_SEC_BE 665 select SYS_FSL_SEC_COMPAT_2 666 select SYS_PPC_E500_USE_DEBUG_TLB 667 668config ARCH_P2041 669 bool 670 select E500MC 671 select FSL_LAW 672 select SYS_FSL_ERRATUM_A004510 673 select SYS_FSL_ERRATUM_A004849 674 select SYS_FSL_ERRATUM_A006261 675 select SYS_FSL_ERRATUM_CPU_A003999 676 select SYS_FSL_ERRATUM_DDR_A003 677 select SYS_FSL_ERRATUM_DDR_A003474 678 select SYS_FSL_ERRATUM_ESDHC111 679 select SYS_FSL_ERRATUM_I2C_A004447 680 select SYS_FSL_ERRATUM_NMG_CPU_A011 681 select SYS_FSL_ERRATUM_SRIO_A004034 682 select SYS_FSL_ERRATUM_USB14 683 select SYS_FSL_HAS_DDR3 684 select SYS_FSL_HAS_SEC 685 select SYS_FSL_QORIQ_CHASSIS1 686 select SYS_FSL_SEC_BE 687 select SYS_FSL_SEC_COMPAT_4 688 689config ARCH_P3041 690 bool 691 select E500MC 692 select FSL_LAW 693 select SYS_FSL_DDR_VER_44 694 select SYS_FSL_ERRATUM_A004510 695 select SYS_FSL_ERRATUM_A004849 696 select SYS_FSL_ERRATUM_A005812 697 select SYS_FSL_ERRATUM_A006261 698 select SYS_FSL_ERRATUM_CPU_A003999 699 select SYS_FSL_ERRATUM_DDR_A003 700 select SYS_FSL_ERRATUM_DDR_A003474 701 select SYS_FSL_ERRATUM_ESDHC111 702 select SYS_FSL_ERRATUM_I2C_A004447 703 select SYS_FSL_ERRATUM_NMG_CPU_A011 704 select SYS_FSL_ERRATUM_SRIO_A004034 705 select SYS_FSL_ERRATUM_USB14 706 select SYS_FSL_HAS_DDR3 707 select SYS_FSL_HAS_SEC 708 select SYS_FSL_QORIQ_CHASSIS1 709 select SYS_FSL_SEC_BE 710 select SYS_FSL_SEC_COMPAT_4 711 712config ARCH_P4080 713 bool 714 select E500MC 715 select FSL_LAW 716 select SYS_FSL_DDR_VER_44 717 select SYS_FSL_ERRATUM_A004510 718 select SYS_FSL_ERRATUM_A004580 719 select SYS_FSL_ERRATUM_A004849 720 select SYS_FSL_ERRATUM_A005812 721 select SYS_FSL_ERRATUM_A007075 722 select SYS_FSL_ERRATUM_CPC_A002 723 select SYS_FSL_ERRATUM_CPC_A003 724 select SYS_FSL_ERRATUM_CPU_A003999 725 select SYS_FSL_ERRATUM_DDR_A003 726 select SYS_FSL_ERRATUM_DDR_A003474 727 select SYS_FSL_ERRATUM_ELBC_A001 728 select SYS_FSL_ERRATUM_ESDHC111 729 select SYS_FSL_ERRATUM_ESDHC13 730 select SYS_FSL_ERRATUM_ESDHC135 731 select SYS_FSL_ERRATUM_I2C_A004447 732 select SYS_FSL_ERRATUM_NMG_CPU_A011 733 select SYS_FSL_ERRATUM_SRIO_A004034 734 select SYS_P4080_ERRATUM_CPU22 735 select SYS_P4080_ERRATUM_PCIE_A003 736 select SYS_P4080_ERRATUM_SERDES8 737 select SYS_P4080_ERRATUM_SERDES9 738 select SYS_P4080_ERRATUM_SERDES_A001 739 select SYS_P4080_ERRATUM_SERDES_A005 740 select SYS_FSL_HAS_DDR3 741 select SYS_FSL_HAS_SEC 742 select SYS_FSL_QORIQ_CHASSIS1 743 select SYS_FSL_SEC_BE 744 select SYS_FSL_SEC_COMPAT_4 745 746config ARCH_P5020 747 bool 748 select E500MC 749 select FSL_LAW 750 select SYS_FSL_DDR_VER_44 751 select SYS_FSL_ERRATUM_A004510 752 select SYS_FSL_ERRATUM_A006261 753 select SYS_FSL_ERRATUM_DDR_A003 754 select SYS_FSL_ERRATUM_DDR_A003474 755 select SYS_FSL_ERRATUM_ESDHC111 756 select SYS_FSL_ERRATUM_I2C_A004447 757 select SYS_FSL_ERRATUM_SRIO_A004034 758 select SYS_FSL_ERRATUM_USB14 759 select SYS_FSL_HAS_DDR3 760 select SYS_FSL_HAS_SEC 761 select SYS_FSL_QORIQ_CHASSIS1 762 select SYS_FSL_SEC_BE 763 select SYS_FSL_SEC_COMPAT_4 764 select SYS_PPC64 765 766config ARCH_P5040 767 bool 768 select E500MC 769 select FSL_LAW 770 select SYS_FSL_DDR_VER_44 771 select SYS_FSL_ERRATUM_A004510 772 select SYS_FSL_ERRATUM_A004699 773 select SYS_FSL_ERRATUM_A005812 774 select SYS_FSL_ERRATUM_A006261 775 select SYS_FSL_ERRATUM_DDR_A003 776 select SYS_FSL_ERRATUM_DDR_A003474 777 select SYS_FSL_ERRATUM_ESDHC111 778 select SYS_FSL_ERRATUM_USB14 779 select SYS_FSL_HAS_DDR3 780 select SYS_FSL_HAS_SEC 781 select SYS_FSL_QORIQ_CHASSIS1 782 select SYS_FSL_SEC_BE 783 select SYS_FSL_SEC_COMPAT_4 784 select SYS_PPC64 785 786config ARCH_QEMU_E500 787 bool 788 789config ARCH_T1023 790 bool 791 select E500MC 792 select FSL_LAW 793 select SYS_FSL_DDR_VER_50 794 select SYS_FSL_ERRATUM_A008378 795 select SYS_FSL_ERRATUM_A009663 796 select SYS_FSL_ERRATUM_A009942 797 select SYS_FSL_ERRATUM_ESDHC111 798 select SYS_FSL_HAS_DDR3 799 select SYS_FSL_HAS_DDR4 800 select SYS_FSL_HAS_SEC 801 select SYS_FSL_QORIQ_CHASSIS2 802 select SYS_FSL_SEC_BE 803 select SYS_FSL_SEC_COMPAT_5 804 select FSL_IFC 805 806config ARCH_T1024 807 bool 808 select E500MC 809 select FSL_LAW 810 select SYS_FSL_DDR_VER_50 811 select SYS_FSL_ERRATUM_A008378 812 select SYS_FSL_ERRATUM_A009663 813 select SYS_FSL_ERRATUM_A009942 814 select SYS_FSL_ERRATUM_ESDHC111 815 select SYS_FSL_HAS_DDR3 816 select SYS_FSL_HAS_DDR4 817 select SYS_FSL_HAS_SEC 818 select SYS_FSL_QORIQ_CHASSIS2 819 select SYS_FSL_SEC_BE 820 select SYS_FSL_SEC_COMPAT_5 821 select FSL_IFC 822 823config ARCH_T1040 824 bool 825 select E500MC 826 select FSL_LAW 827 select SYS_FSL_DDR_VER_50 828 select SYS_FSL_ERRATUM_A008044 829 select SYS_FSL_ERRATUM_A008378 830 select SYS_FSL_ERRATUM_A009663 831 select SYS_FSL_ERRATUM_A009942 832 select SYS_FSL_ERRATUM_ESDHC111 833 select SYS_FSL_HAS_DDR3 834 select SYS_FSL_HAS_DDR4 835 select SYS_FSL_HAS_SEC 836 select SYS_FSL_QORIQ_CHASSIS2 837 select SYS_FSL_SEC_BE 838 select SYS_FSL_SEC_COMPAT_5 839 select FSL_IFC 840 841config ARCH_T1042 842 bool 843 select E500MC 844 select FSL_LAW 845 select SYS_FSL_DDR_VER_50 846 select SYS_FSL_ERRATUM_A008044 847 select SYS_FSL_ERRATUM_A008378 848 select SYS_FSL_ERRATUM_A009663 849 select SYS_FSL_ERRATUM_A009942 850 select SYS_FSL_ERRATUM_ESDHC111 851 select SYS_FSL_HAS_DDR3 852 select SYS_FSL_HAS_DDR4 853 select SYS_FSL_HAS_SEC 854 select SYS_FSL_QORIQ_CHASSIS2 855 select SYS_FSL_SEC_BE 856 select SYS_FSL_SEC_COMPAT_5 857 select FSL_IFC 858 859config ARCH_T2080 860 bool 861 select E500MC 862 select E6500 863 select FSL_LAW 864 select SYS_FSL_DDR_VER_47 865 select SYS_FSL_ERRATUM_A006379 866 select SYS_FSL_ERRATUM_A006593 867 select SYS_FSL_ERRATUM_A007186 868 select SYS_FSL_ERRATUM_A007212 869 select SYS_FSL_ERRATUM_A007815 870 select SYS_FSL_ERRATUM_A007907 871 select SYS_FSL_ERRATUM_A009942 872 select SYS_FSL_ERRATUM_ESDHC111 873 select SYS_FSL_HAS_DDR3 874 select SYS_FSL_HAS_SEC 875 select SYS_FSL_QORIQ_CHASSIS2 876 select SYS_FSL_SEC_BE 877 select SYS_FSL_SEC_COMPAT_4 878 select SYS_PPC64 879 select FSL_IFC 880 881config ARCH_T2081 882 bool 883 select E500MC 884 select E6500 885 select FSL_LAW 886 select SYS_FSL_DDR_VER_47 887 select SYS_FSL_ERRATUM_A006379 888 select SYS_FSL_ERRATUM_A006593 889 select SYS_FSL_ERRATUM_A007186 890 select SYS_FSL_ERRATUM_A007212 891 select SYS_FSL_ERRATUM_A009942 892 select SYS_FSL_ERRATUM_ESDHC111 893 select SYS_FSL_HAS_DDR3 894 select SYS_FSL_HAS_SEC 895 select SYS_FSL_QORIQ_CHASSIS2 896 select SYS_FSL_SEC_BE 897 select SYS_FSL_SEC_COMPAT_4 898 select SYS_PPC64 899 select FSL_IFC 900 901config ARCH_T4160 902 bool 903 select E500MC 904 select E6500 905 select FSL_LAW 906 select SYS_FSL_DDR_VER_47 907 select SYS_FSL_ERRATUM_A004468 908 select SYS_FSL_ERRATUM_A005871 909 select SYS_FSL_ERRATUM_A006379 910 select SYS_FSL_ERRATUM_A006593 911 select SYS_FSL_ERRATUM_A007186 912 select SYS_FSL_ERRATUM_A007798 913 select SYS_FSL_ERRATUM_A009942 914 select SYS_FSL_HAS_DDR3 915 select SYS_FSL_HAS_SEC 916 select SYS_FSL_QORIQ_CHASSIS2 917 select SYS_FSL_SEC_BE 918 select SYS_FSL_SEC_COMPAT_4 919 select SYS_PPC64 920 select FSL_IFC 921 922config ARCH_T4240 923 bool 924 select E500MC 925 select E6500 926 select FSL_LAW 927 select SYS_FSL_DDR_VER_47 928 select SYS_FSL_ERRATUM_A004468 929 select SYS_FSL_ERRATUM_A005871 930 select SYS_FSL_ERRATUM_A006261 931 select SYS_FSL_ERRATUM_A006379 932 select SYS_FSL_ERRATUM_A006593 933 select SYS_FSL_ERRATUM_A007186 934 select SYS_FSL_ERRATUM_A007798 935 select SYS_FSL_ERRATUM_A007815 936 select SYS_FSL_ERRATUM_A007907 937 select SYS_FSL_ERRATUM_A009942 938 select SYS_FSL_HAS_DDR3 939 select SYS_FSL_HAS_SEC 940 select SYS_FSL_QORIQ_CHASSIS2 941 select SYS_FSL_SEC_BE 942 select SYS_FSL_SEC_COMPAT_4 943 select SYS_PPC64 944 select FSL_IFC 945 946config BOOKE 947 bool 948 default y 949 950config E500 951 bool 952 default y 953 help 954 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 955 956config E500MC 957 bool 958 help 959 Enble PowerPC E500MC core 960 961config E6500 962 bool 963 help 964 Enable PowerPC E6500 core 965 966config FSL_LAW 967 bool 968 help 969 Use Freescale common code for Local Access Window 970 971config SECURE_BOOT 972 bool "Secure Boot" 973 help 974 Enable Freescale Secure Boot feature. Normally selected 975 by defconfig. If unsure, do not change. 976 977config MAX_CPUS 978 int "Maximum number of CPUs permitted for MPC85xx" 979 default 12 if ARCH_T4240 980 default 8 if ARCH_P4080 || \ 981 ARCH_T4160 982 default 4 if ARCH_B4860 || \ 983 ARCH_P2041 || \ 984 ARCH_P3041 || \ 985 ARCH_P5040 || \ 986 ARCH_T1040 || \ 987 ARCH_T1042 || \ 988 ARCH_T2080 || \ 989 ARCH_T2081 990 default 2 if ARCH_B4420 || \ 991 ARCH_BSC9132 || \ 992 ARCH_MPC8572 || \ 993 ARCH_P1020 || \ 994 ARCH_P1021 || \ 995 ARCH_P1022 || \ 996 ARCH_P1023 || \ 997 ARCH_P1024 || \ 998 ARCH_P1025 || \ 999 ARCH_P2020 || \ 1000 ARCH_P5020 || \ 1001 ARCH_T1023 || \ 1002 ARCH_T1024 1003 default 1 1004 help 1005 Set this number to the maximum number of possible CPUs in the SoC. 1006 SoCs may have multiple clusters with each cluster may have multiple 1007 ports. If some ports are reserved but higher ports are used for 1008 cores, count the reserved ports. This will allocate enough memory 1009 in spin table to properly handle all cores. 1010 1011config SYS_CCSRBAR_DEFAULT 1012 hex "Default CCSRBAR address" 1013 default 0xff700000 if ARCH_BSC9131 || \ 1014 ARCH_BSC9132 || \ 1015 ARCH_C29X || \ 1016 ARCH_MPC8536 || \ 1017 ARCH_MPC8540 || \ 1018 ARCH_MPC8541 || \ 1019 ARCH_MPC8544 || \ 1020 ARCH_MPC8548 || \ 1021 ARCH_MPC8555 || \ 1022 ARCH_MPC8560 || \ 1023 ARCH_MPC8568 || \ 1024 ARCH_MPC8569 || \ 1025 ARCH_MPC8572 || \ 1026 ARCH_P1010 || \ 1027 ARCH_P1011 || \ 1028 ARCH_P1020 || \ 1029 ARCH_P1021 || \ 1030 ARCH_P1022 || \ 1031 ARCH_P1024 || \ 1032 ARCH_P1025 || \ 1033 ARCH_P2020 1034 default 0xff600000 if ARCH_P1023 1035 default 0xfe000000 if ARCH_B4420 || \ 1036 ARCH_B4860 || \ 1037 ARCH_P2041 || \ 1038 ARCH_P3041 || \ 1039 ARCH_P4080 || \ 1040 ARCH_P5020 || \ 1041 ARCH_P5040 || \ 1042 ARCH_T1023 || \ 1043 ARCH_T1024 || \ 1044 ARCH_T1040 || \ 1045 ARCH_T1042 || \ 1046 ARCH_T2080 || \ 1047 ARCH_T2081 || \ 1048 ARCH_T4160 || \ 1049 ARCH_T4240 1050 default 0xe0000000 if ARCH_QEMU_E500 1051 help 1052 Default value of CCSRBAR comes from power-on-reset. It 1053 is fixed on each SoC. Some SoCs can have different value 1054 if changed by pre-boot regime. The value here must match 1055 the current value in SoC. If not sure, do not change. 1056 1057config SYS_FSL_ERRATUM_A004468 1058 bool 1059 1060config SYS_FSL_ERRATUM_A004477 1061 bool 1062 1063config SYS_FSL_ERRATUM_A004508 1064 bool 1065 1066config SYS_FSL_ERRATUM_A004580 1067 bool 1068 1069config SYS_FSL_ERRATUM_A004699 1070 bool 1071 1072config SYS_FSL_ERRATUM_A004849 1073 bool 1074 1075config SYS_FSL_ERRATUM_A004510 1076 bool 1077 1078config SYS_FSL_ERRATUM_A004510_SVR_REV 1079 hex 1080 depends on SYS_FSL_ERRATUM_A004510 1081 default 0x20 if ARCH_P4080 1082 default 0x10 1083 1084config SYS_FSL_ERRATUM_A004510_SVR_REV2 1085 hex 1086 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1087 default 0x11 1088 1089config SYS_FSL_ERRATUM_A005125 1090 bool 1091 1092config SYS_FSL_ERRATUM_A005434 1093 bool 1094 1095config SYS_FSL_ERRATUM_A005812 1096 bool 1097 1098config SYS_FSL_ERRATUM_A005871 1099 bool 1100 1101config SYS_FSL_ERRATUM_A006261 1102 bool 1103 1104config SYS_FSL_ERRATUM_A006379 1105 bool 1106 1107config SYS_FSL_ERRATUM_A006384 1108 bool 1109 1110config SYS_FSL_ERRATUM_A006475 1111 bool 1112 1113config SYS_FSL_ERRATUM_A006593 1114 bool 1115 1116config SYS_FSL_ERRATUM_A007075 1117 bool 1118 1119config SYS_FSL_ERRATUM_A007186 1120 bool 1121 1122config SYS_FSL_ERRATUM_A007212 1123 bool 1124 1125config SYS_FSL_ERRATUM_A007815 1126 bool 1127 1128config SYS_FSL_ERRATUM_A007798 1129 bool 1130 1131config SYS_FSL_ERRATUM_A007907 1132 bool 1133 1134config SYS_FSL_ERRATUM_A008044 1135 bool 1136 1137config SYS_FSL_ERRATUM_CPC_A002 1138 bool 1139 1140config SYS_FSL_ERRATUM_CPC_A003 1141 bool 1142 1143config SYS_FSL_ERRATUM_CPU_A003999 1144 bool 1145 1146config SYS_FSL_ERRATUM_ELBC_A001 1147 bool 1148 1149config SYS_FSL_ERRATUM_I2C_A004447 1150 bool 1151 1152config SYS_FSL_A004447_SVR_REV 1153 hex 1154 depends on SYS_FSL_ERRATUM_I2C_A004447 1155 default 0x00 if ARCH_MPC8548 1156 default 0x10 if ARCH_P1010 1157 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1158 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1159 1160config SYS_FSL_ERRATUM_IFC_A002769 1161 bool 1162 1163config SYS_FSL_ERRATUM_IFC_A003399 1164 bool 1165 1166config SYS_FSL_ERRATUM_NMG_CPU_A011 1167 bool 1168 1169config SYS_FSL_ERRATUM_NMG_ETSEC129 1170 bool 1171 1172config SYS_FSL_ERRATUM_NMG_LBC103 1173 bool 1174 1175config SYS_FSL_ERRATUM_P1010_A003549 1176 bool 1177 1178config SYS_FSL_ERRATUM_SATA_A001 1179 bool 1180 1181config SYS_FSL_ERRATUM_SEC_A003571 1182 bool 1183 1184config SYS_FSL_ERRATUM_SRIO_A004034 1185 bool 1186 1187config SYS_FSL_ERRATUM_USB14 1188 bool 1189 1190config SYS_P4080_ERRATUM_CPU22 1191 bool 1192 1193config SYS_P4080_ERRATUM_PCIE_A003 1194 bool 1195 1196config SYS_P4080_ERRATUM_SERDES8 1197 bool 1198 1199config SYS_P4080_ERRATUM_SERDES9 1200 bool 1201 1202config SYS_P4080_ERRATUM_SERDES_A001 1203 bool 1204 1205config SYS_P4080_ERRATUM_SERDES_A005 1206 bool 1207 1208config SYS_FSL_QORIQ_CHASSIS1 1209 bool 1210 1211config SYS_FSL_QORIQ_CHASSIS2 1212 bool 1213 1214config SYS_FSL_NUM_LAWS 1215 int "Number of local access windows" 1216 depends on FSL_LAW 1217 default 32 if ARCH_B4420 || \ 1218 ARCH_B4860 || \ 1219 ARCH_P2041 || \ 1220 ARCH_P3041 || \ 1221 ARCH_P4080 || \ 1222 ARCH_P5020 || \ 1223 ARCH_P5040 || \ 1224 ARCH_T2080 || \ 1225 ARCH_T2081 || \ 1226 ARCH_T4160 || \ 1227 ARCH_T4240 1228 default 16 if ARCH_T1023 || \ 1229 ARCH_T1024 || \ 1230 ARCH_T1040 || \ 1231 ARCH_T1042 1232 default 12 if ARCH_BSC9131 || \ 1233 ARCH_BSC9132 || \ 1234 ARCH_C29X || \ 1235 ARCH_MPC8536 || \ 1236 ARCH_MPC8572 || \ 1237 ARCH_P1010 || \ 1238 ARCH_P1011 || \ 1239 ARCH_P1020 || \ 1240 ARCH_P1021 || \ 1241 ARCH_P1022 || \ 1242 ARCH_P1023 || \ 1243 ARCH_P1024 || \ 1244 ARCH_P1025 || \ 1245 ARCH_P2020 1246 default 10 if ARCH_MPC8544 || \ 1247 ARCH_MPC8548 || \ 1248 ARCH_MPC8568 || \ 1249 ARCH_MPC8569 1250 default 8 if ARCH_MPC8540 || \ 1251 ARCH_MPC8541 || \ 1252 ARCH_MPC8555 || \ 1253 ARCH_MPC8560 1254 help 1255 Number of local access windows. This is fixed per SoC. 1256 If not sure, do not change. 1257 1258config SYS_FSL_THREADS_PER_CORE 1259 int 1260 default 2 if E6500 1261 default 1 1262 1263config SYS_NUM_TLBCAMS 1264 int "Number of TLB CAM entries" 1265 default 64 if E500MC 1266 default 16 1267 help 1268 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1269 16 for other E500 SoCs. 1270 1271config SYS_PPC64 1272 bool 1273 1274config SYS_PPC_E500_USE_DEBUG_TLB 1275 bool 1276 1277config FSL_IFC 1278 bool 1279 1280config SYS_PPC_E500_DEBUG_TLB 1281 int "Temporary TLB entry for external debugger" 1282 depends on SYS_PPC_E500_USE_DEBUG_TLB 1283 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1284 default 1 if ARCH_MPC8536 1285 default 2 if ARCH_MPC8572 || \ 1286 ARCH_P1011 || \ 1287 ARCH_P1020 || \ 1288 ARCH_P1021 || \ 1289 ARCH_P1022 || \ 1290 ARCH_P1024 || \ 1291 ARCH_P1025 || \ 1292 ARCH_P2020 1293 default 3 if ARCH_P1010 || \ 1294 ARCH_BSC9132 || \ 1295 ARCH_C29X 1296 help 1297 Select a temporary TLB entry to be used during boot to work 1298 around limitations in e500v1 and e500v2 external debugger 1299 support. This reduces the portions of the boot code where 1300 breakpoints and single stepping do not work. The value of this 1301 symbol should be set to the TLB1 entry to be used for this 1302 purpose. If unsure, do not change. 1303 1304source "board/freescale/b4860qds/Kconfig" 1305source "board/freescale/bsc9131rdb/Kconfig" 1306source "board/freescale/bsc9132qds/Kconfig" 1307source "board/freescale/c29xpcie/Kconfig" 1308source "board/freescale/corenet_ds/Kconfig" 1309source "board/freescale/mpc8536ds/Kconfig" 1310source "board/freescale/mpc8540ads/Kconfig" 1311source "board/freescale/mpc8541cds/Kconfig" 1312source "board/freescale/mpc8544ds/Kconfig" 1313source "board/freescale/mpc8548cds/Kconfig" 1314source "board/freescale/mpc8555cds/Kconfig" 1315source "board/freescale/mpc8560ads/Kconfig" 1316source "board/freescale/mpc8568mds/Kconfig" 1317source "board/freescale/mpc8569mds/Kconfig" 1318source "board/freescale/mpc8572ds/Kconfig" 1319source "board/freescale/p1010rdb/Kconfig" 1320source "board/freescale/p1022ds/Kconfig" 1321source "board/freescale/p1023rdb/Kconfig" 1322source "board/freescale/p1_p2_rdb_pc/Kconfig" 1323source "board/freescale/p1_twr/Kconfig" 1324source "board/freescale/p2041rdb/Kconfig" 1325source "board/freescale/qemu-ppce500/Kconfig" 1326source "board/freescale/t102xqds/Kconfig" 1327source "board/freescale/t102xrdb/Kconfig" 1328source "board/freescale/t1040qds/Kconfig" 1329source "board/freescale/t104xrdb/Kconfig" 1330source "board/freescale/t208xqds/Kconfig" 1331source "board/freescale/t208xrdb/Kconfig" 1332source "board/freescale/t4qds/Kconfig" 1333source "board/freescale/t4rdb/Kconfig" 1334source "board/gdsys/p1022/Kconfig" 1335source "board/keymile/kmp204x/Kconfig" 1336source "board/sbc8548/Kconfig" 1337source "board/socrates/Kconfig" 1338source "board/varisys/cyrus/Kconfig" 1339source "board/xes/xpedite520x/Kconfig" 1340source "board/xes/xpedite537x/Kconfig" 1341source "board/xes/xpedite550x/Kconfig" 1342source "board/Arcturus/ucp1020/Kconfig" 1343 1344endmenu 1345