1a47a12beSStefan Roese/* 2a47a12beSStefan Roese * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3a47a12beSStefan Roese * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4a47a12beSStefan Roese * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5a47a12beSStefan Roese * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6a47a12beSStefan Roese * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8a47a12beSStefan Roese */ 9a47a12beSStefan Roese 10a47a12beSStefan Roese/* 11a47a12beSStefan Roese * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 12a47a12beSStefan Roese */ 13a47a12beSStefan Roese 1425ddd1fbSWolfgang Denk#include <asm-offsets.h> 15a47a12beSStefan Roese#include <config.h> 16a47a12beSStefan Roese#include <mpc83xx.h> 1709c2e90cSAndreas Bießmann#ifndef CONFIG_IDENT_STRING 1809c2e90cSAndreas Bießmann#define CONFIG_IDENT_STRING "MPC83XX" 1909c2e90cSAndreas Bießmann#endif 20a47a12beSStefan Roese#include <version.h> 21a47a12beSStefan Roese 22a47a12beSStefan Roese#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 23a47a12beSStefan Roese#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 24a47a12beSStefan Roese 25a47a12beSStefan Roese#include <ppc_asm.tmpl> 26a47a12beSStefan Roese#include <ppc_defs.h> 27a47a12beSStefan Roese 28a47a12beSStefan Roese#include <asm/cache.h> 29a47a12beSStefan Roese#include <asm/mmu.h> 30d98b0523SPeter Tyser#include <asm/u-boot.h> 31a47a12beSStefan Roese 32a47a12beSStefan Roese/* We don't want the MMU yet. 33a47a12beSStefan Roese */ 34a47a12beSStefan Roese#undef MSR_KERNEL 35a47a12beSStefan Roese 36a47a12beSStefan Roese/* 37a47a12beSStefan Roese * Floating Point enable, Machine Check and Recoverable Interr. 38a47a12beSStefan Roese */ 39a47a12beSStefan Roese#ifdef DEBUG 40a47a12beSStefan Roese#define MSR_KERNEL (MSR_FP|MSR_RI) 41a47a12beSStefan Roese#else 42a47a12beSStefan Roese#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 43a47a12beSStefan Roese#endif 44a47a12beSStefan Roese 4506f60ae3SScott Wood#if defined(CONFIG_NAND_SPL) || \ 4606f60ae3SScott Wood (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) 4706f60ae3SScott Wood#define MINIMAL_SPL 4806f60ae3SScott Wood#endif 4906f60ae3SScott Wood 5006f60ae3SScott Wood#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ 5106f60ae3SScott Wood !defined(CONFIG_SYS_RAMBOOT) 52a47a12beSStefan Roese#define CONFIG_SYS_FLASHBOOT 53a47a12beSStefan Roese#endif 54a47a12beSStefan Roese 55a47a12beSStefan Roese/* 56a47a12beSStefan Roese * Set up GOT: Global Offset Table 57a47a12beSStefan Roese * 58a47a12beSStefan Roese * Use r12 to access the GOT 59a47a12beSStefan Roese */ 60a47a12beSStefan Roese START_GOT 61a47a12beSStefan Roese GOT_ENTRY(_GOT2_TABLE_) 62a47a12beSStefan Roese GOT_ENTRY(__bss_start) 633929fb0aSSimon Glass GOT_ENTRY(__bss_end) 64a47a12beSStefan Roese 6506f60ae3SScott Wood#ifndef MINIMAL_SPL 66a47a12beSStefan Roese GOT_ENTRY(_FIXUP_TABLE_) 67a47a12beSStefan Roese GOT_ENTRY(_start) 68a47a12beSStefan Roese GOT_ENTRY(_start_of_vectors) 69a47a12beSStefan Roese GOT_ENTRY(_end_of_vectors) 70a47a12beSStefan Roese GOT_ENTRY(transfer_to_handler) 71a47a12beSStefan Roese#endif 72a47a12beSStefan Roese END_GOT 73a47a12beSStefan Roese 74a47a12beSStefan Roese/* 75a47a12beSStefan Roese * The Hard Reset Configuration Word (HRCW) table is in the first 64 76a47a12beSStefan Roese * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 77a47a12beSStefan Roese * times so the processor can fetch it out of flash whether the flash 78a47a12beSStefan Roese * is 8, 16, 32, or 64 bits wide (hardware trickery). 79a47a12beSStefan Roese */ 80a47a12beSStefan Roese .text 81a47a12beSStefan Roese#define _HRCW_TABLE_ENTRY(w) \ 82a47a12beSStefan Roese .fill 8,1,(((w)>>24)&0xff); \ 83a47a12beSStefan Roese .fill 8,1,(((w)>>16)&0xff); \ 84a47a12beSStefan Roese .fill 8,1,(((w)>> 8)&0xff); \ 85a47a12beSStefan Roese .fill 8,1,(((w) )&0xff) 86a47a12beSStefan Roese 87a47a12beSStefan Roese _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 88a47a12beSStefan Roese _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 89a47a12beSStefan Roese 90a47a12beSStefan Roese/* 91a47a12beSStefan Roese * Magic number and version string - put it after the HRCW since it 92a47a12beSStefan Roese * cannot be first in flash like it is in many other processors. 93a47a12beSStefan Roese */ 94a47a12beSStefan Roese .long 0x27051956 /* U-Boot Magic Number */ 95a47a12beSStefan Roese 96a47a12beSStefan Roese .globl version_string 97a47a12beSStefan Roeseversion_string: 9809c2e90cSAndreas Bießmann .ascii U_BOOT_VERSION_STRING, "\0" 99a47a12beSStefan Roese 100a47a12beSStefan Roese .align 2 101a47a12beSStefan Roese 102a47a12beSStefan Roese .globl enable_addr_trans 103a47a12beSStefan Roeseenable_addr_trans: 104a47a12beSStefan Roese /* enable address translation */ 105a47a12beSStefan Roese mfmsr r5 106a47a12beSStefan Roese ori r5, r5, (MSR_IR | MSR_DR) 107a47a12beSStefan Roese mtmsr r5 108a47a12beSStefan Roese isync 109a47a12beSStefan Roese blr 110a47a12beSStefan Roese 111a47a12beSStefan Roese .globl disable_addr_trans 112a47a12beSStefan Roesedisable_addr_trans: 113a47a12beSStefan Roese /* disable address translation */ 114a47a12beSStefan Roese mflr r4 115a47a12beSStefan Roese mfmsr r3 116a47a12beSStefan Roese andi. r0, r3, (MSR_IR | MSR_DR) 117a47a12beSStefan Roese beqlr 118a47a12beSStefan Roese andc r3, r3, r0 119a47a12beSStefan Roese mtspr SRR0, r4 120a47a12beSStefan Roese mtspr SRR1, r3 121a47a12beSStefan Roese rfi 122a47a12beSStefan Roese 123*3f283f4bSRamneek Mehresh .globl get_svr 124*3f283f4bSRamneek Mehreshget_svr: 125*3f283f4bSRamneek Mehresh mfspr r3, SVR 126*3f283f4bSRamneek Mehresh blr 127*3f283f4bSRamneek Mehresh 128a47a12beSStefan Roese .globl get_pvr 129a47a12beSStefan Roeseget_pvr: 130a47a12beSStefan Roese mfspr r3, PVR 131a47a12beSStefan Roese blr 132a47a12beSStefan Roese 133a47a12beSStefan Roese .globl ppcDWstore 134a47a12beSStefan RoeseppcDWstore: 135a47a12beSStefan Roese lfd 1, 0(r4) 136a47a12beSStefan Roese stfd 1, 0(r3) 137a47a12beSStefan Roese blr 138a47a12beSStefan Roese 139a47a12beSStefan Roese .globl ppcDWload 140a47a12beSStefan RoeseppcDWload: 141a47a12beSStefan Roese lfd 1, 0(r3) 142a47a12beSStefan Roese stfd 1, 0(r4) 143a47a12beSStefan Roese blr 144a47a12beSStefan Roese 145a47a12beSStefan Roese#ifndef CONFIG_DEFAULT_IMMR 146a47a12beSStefan Roese#error CONFIG_DEFAULT_IMMR must be defined 147a47a12beSStefan Roese#endif /* CONFIG_SYS_DEFAULT_IMMR */ 148a47a12beSStefan Roese#ifndef CONFIG_SYS_IMMR 149a47a12beSStefan Roese#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 150a47a12beSStefan Roese#endif /* CONFIG_SYS_IMMR */ 151a47a12beSStefan Roese 152a47a12beSStefan Roese/* 153a47a12beSStefan Roese * After configuration, a system reset exception is executed using the 154a47a12beSStefan Roese * vector at offset 0x100 relative to the base set by MSR[IP]. If 155a47a12beSStefan Roese * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 156a47a12beSStefan Roese * base address is 0xfff00000. In the case of a Power On Reset or Hard 157a47a12beSStefan Roese * Reset, the value of MSR[IP] is determined by the CIP field in the 158a47a12beSStefan Roese * HRCW. 159a47a12beSStefan Roese * 160a47a12beSStefan Roese * Other bits in the HRCW set up the Base Address and Port Size in BR0. 161a47a12beSStefan Roese * This determines the location of the boot ROM (flash or EPROM) in the 162a47a12beSStefan Roese * processor's address space at boot time. As long as the HRCW is set up 163a47a12beSStefan Roese * so that we eventually end up executing the code below when the 164a47a12beSStefan Roese * processor executes the reset exception, the actual values used should 165a47a12beSStefan Roese * not matter. 166a47a12beSStefan Roese * 167a47a12beSStefan Roese * Once we have got here, the address mask in OR0 is cleared so that the 168a47a12beSStefan Roese * bottom 32K of the boot ROM is effectively repeated all throughout the 169a47a12beSStefan Roese * processor's address space, after which we can jump to the absolute 170a47a12beSStefan Roese * address at which the boot ROM was linked at compile time, and proceed 171a47a12beSStefan Roese * to initialise the memory controller without worrying if the rug will 172a47a12beSStefan Roese * be pulled out from under us, so to speak (it will be fine as long as 173a47a12beSStefan Roese * we configure BR0 with the same boot ROM link address). 174a47a12beSStefan Roese */ 175a47a12beSStefan Roese . = EXC_OFF_SYS_RESET 176a47a12beSStefan Roese 177a47a12beSStefan Roese .globl _start 178a47a12beSStefan Roese_start: /* time t 0 */ 179a47a12beSStefan Roese lis r4, CONFIG_DEFAULT_IMMR@h 180a47a12beSStefan Roese nop 18152ebd9c1SPeter Tyser 182a47a12beSStefan Roese mfmsr r5 /* save msr contents */ 183a47a12beSStefan Roese 184a47a12beSStefan Roese /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 185a47a12beSStefan Roese bl 1f 186a47a12beSStefan Roese1: mflr r7 187a47a12beSStefan Roese 188a47a12beSStefan Roese lis r3, CONFIG_SYS_IMMR@h 189a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IMMR@l 190a47a12beSStefan Roese 191a47a12beSStefan Roese lwz r6, IMMRBAR(r4) 192a47a12beSStefan Roese isync 193a47a12beSStefan Roese 194a47a12beSStefan Roese stw r3, IMMRBAR(r4) 195a47a12beSStefan Roese lwz r6, 0(r7) /* Arbitrary external load */ 196a47a12beSStefan Roese isync 197a47a12beSStefan Roese 198a47a12beSStefan Roese lwz r6, IMMRBAR(r3) 199a47a12beSStefan Roese isync 200a47a12beSStefan Roese 201a47a12beSStefan Roese /* Initialise the E300 processor core */ 202a47a12beSStefan Roese /*------------------------------------------*/ 203a47a12beSStefan Roese 20406f60ae3SScott Wood#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ 20506f60ae3SScott Wood defined(CONFIG_NAND_SPL) 206a47a12beSStefan Roese /* The FCM begins execution after only the first page 207a47a12beSStefan Roese * is loaded. Wait for the rest before branching 208a47a12beSStefan Roese * to another flash page. 209a47a12beSStefan Roese */ 210a47a12beSStefan Roese1: lwz r6, 0x50b0(r3) 211a47a12beSStefan Roese andi. r6, r6, 1 212a47a12beSStefan Roese beq 1b 213a47a12beSStefan Roese#endif 214a47a12beSStefan Roese 215a47a12beSStefan Roese bl init_e300_core 216a47a12beSStefan Roese 217a47a12beSStefan Roese#ifdef CONFIG_SYS_FLASHBOOT 218a47a12beSStefan Roese 219a47a12beSStefan Roese /* Inflate flash location so it appears everywhere, calculate */ 220a47a12beSStefan Roese /* the absolute address in final location of the FLASH, jump */ 221a47a12beSStefan Roese /* there and deflate the flash size back to minimal size */ 222a47a12beSStefan Roese /*------------------------------------------------------------*/ 223a47a12beSStefan Roese bl map_flash_by_law1 224a47a12beSStefan Roese lis r4, (CONFIG_SYS_MONITOR_BASE)@h 225a47a12beSStefan Roese ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 226a47a12beSStefan Roese addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 227a47a12beSStefan Roese mtlr r5 228a47a12beSStefan Roese blr 229a47a12beSStefan Roesein_flash: 230a47a12beSStefan Roese#if 1 /* Remapping flash with LAW0. */ 231a47a12beSStefan Roese bl remap_flash_by_law0 232a47a12beSStefan Roese#endif 233a47a12beSStefan Roese#endif /* CONFIG_SYS_FLASHBOOT */ 234a47a12beSStefan Roese 235a47a12beSStefan Roese /* setup the bats */ 236a47a12beSStefan Roese bl setup_bats 237a47a12beSStefan Roese sync 238a47a12beSStefan Roese 239a47a12beSStefan Roese /* 240a47a12beSStefan Roese * Cache must be enabled here for stack-in-cache trick. 241a47a12beSStefan Roese * This means we need to enable the BATS. 242a47a12beSStefan Roese * This means: 243a47a12beSStefan Roese * 1) for the EVB, original gt regs need to be mapped 244a47a12beSStefan Roese * 2) need to have an IBAT for the 0xf region, 245a47a12beSStefan Roese * we are running there! 246a47a12beSStefan Roese * Cache should be turned on after BATs, since by default 247a47a12beSStefan Roese * everything is write-through. 248a47a12beSStefan Roese * The init-mem BAT can be reused after reloc. The old 249a47a12beSStefan Roese * gt-regs BAT can be reused after board_init_f calls 250a47a12beSStefan Roese * board_early_init_f (EVB only). 251a47a12beSStefan Roese */ 252a47a12beSStefan Roese /* enable address translation */ 253a47a12beSStefan Roese bl enable_addr_trans 254a47a12beSStefan Roese sync 255a47a12beSStefan Roese 256a47a12beSStefan Roese /* enable the data cache */ 257a47a12beSStefan Roese bl dcache_enable 258a47a12beSStefan Roese sync 259a47a12beSStefan Roese#ifdef CONFIG_SYS_INIT_RAM_LOCK 260a47a12beSStefan Roese bl lock_ram_in_cache 261a47a12beSStefan Roese sync 262a47a12beSStefan Roese#endif 263a47a12beSStefan Roese 264a47a12beSStefan Roese /* set up the stack pointer in our newly created 265a47a12beSStefan Roese * cache-ram (r1) */ 266a47a12beSStefan Roese lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 267a47a12beSStefan Roese ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 268a47a12beSStefan Roese 269a47a12beSStefan Roese li r0, 0 /* Make room for stack frame header and */ 270a47a12beSStefan Roese stwu r0, -4(r1) /* clear final stack frame so that */ 271a47a12beSStefan Roese stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 272a47a12beSStefan Roese 273a47a12beSStefan Roese 274a47a12beSStefan Roese /* let the C-code set up the rest */ 275a47a12beSStefan Roese /* */ 276a47a12beSStefan Roese /* Be careful to keep code relocatable & stack humble */ 277a47a12beSStefan Roese /*------------------------------------------------------*/ 278a47a12beSStefan Roese 279a47a12beSStefan Roese GET_GOT /* initialize GOT access */ 2808c4734e9SWolfgang Denk 281a47a12beSStefan Roese /* r3: IMMR */ 282a47a12beSStefan Roese lis r3, CONFIG_SYS_IMMR@h 283a47a12beSStefan Roese /* run low-level CPU init code (in Flash)*/ 284a47a12beSStefan Roese bl cpu_init_f 285a47a12beSStefan Roese 286a47a12beSStefan Roese /* run 1st part of board init code (in Flash)*/ 287a47a12beSStefan Roese bl board_init_f 288a47a12beSStefan Roese 28952ebd9c1SPeter Tyser /* NOTREACHED - board_init_f() does not return */ 29052ebd9c1SPeter Tyser 29106f60ae3SScott Wood#ifndef MINIMAL_SPL 292a47a12beSStefan Roese/* 293a47a12beSStefan Roese * Vector Table 294a47a12beSStefan Roese */ 295a47a12beSStefan Roese 296a47a12beSStefan Roese .globl _start_of_vectors 297a47a12beSStefan Roese_start_of_vectors: 298a47a12beSStefan Roese 299a47a12beSStefan Roese/* Machine check */ 300a47a12beSStefan Roese STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 301a47a12beSStefan Roese 302a47a12beSStefan Roese/* Data Storage exception. */ 303a47a12beSStefan Roese STD_EXCEPTION(0x300, DataStorage, UnknownException) 304a47a12beSStefan Roese 305a47a12beSStefan Roese/* Instruction Storage exception. */ 306a47a12beSStefan Roese STD_EXCEPTION(0x400, InstStorage, UnknownException) 307a47a12beSStefan Roese 308a47a12beSStefan Roese/* External Interrupt exception. */ 309a47a12beSStefan Roese#ifndef FIXME 310a47a12beSStefan Roese STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 311a47a12beSStefan Roese#endif 312a47a12beSStefan Roese 313a47a12beSStefan Roese/* Alignment exception. */ 314a47a12beSStefan Roese . = 0x600 315a47a12beSStefan RoeseAlignment: 316a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 317a47a12beSStefan Roese mfspr r4,DAR 318a47a12beSStefan Roese stw r4,_DAR(r21) 319a47a12beSStefan Roese mfspr r5,DSISR 320a47a12beSStefan Roese stw r5,_DSISR(r21) 321a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 322a47a12beSStefan Roese EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 323a47a12beSStefan Roese 324a47a12beSStefan Roese/* Program check exception */ 325a47a12beSStefan Roese . = 0x700 326a47a12beSStefan RoeseProgramCheck: 327a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 328a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 329a47a12beSStefan Roese EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 330a47a12beSStefan Roese MSR_KERNEL, COPY_EE) 331a47a12beSStefan Roese 332a47a12beSStefan Roese STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 333a47a12beSStefan Roese 334a47a12beSStefan Roese /* I guess we could implement decrementer, and may have 335a47a12beSStefan Roese * to someday for timekeeping. 336a47a12beSStefan Roese */ 337a47a12beSStefan Roese STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 338a47a12beSStefan Roese 339a47a12beSStefan Roese STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 340a47a12beSStefan Roese STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 341a47a12beSStefan Roese STD_EXCEPTION(0xc00, SystemCall, UnknownException) 342a47a12beSStefan Roese STD_EXCEPTION(0xd00, SingleStep, UnknownException) 343a47a12beSStefan Roese 344a47a12beSStefan Roese STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 345a47a12beSStefan Roese STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 346a47a12beSStefan Roese 347a47a12beSStefan Roese STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 348a47a12beSStefan Roese STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 349a47a12beSStefan Roese STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 350a47a12beSStefan Roese#ifdef DEBUG 351a47a12beSStefan Roese . = 0x1300 352a47a12beSStefan Roese /* 353a47a12beSStefan Roese * This exception occurs when the program counter matches the 354a47a12beSStefan Roese * Instruction Address Breakpoint Register (IABR). 355a47a12beSStefan Roese * 356a47a12beSStefan Roese * I want the cpu to halt if this occurs so I can hunt around 357a47a12beSStefan Roese * with the debugger and look at things. 358a47a12beSStefan Roese * 359a47a12beSStefan Roese * When DEBUG is defined, both machine check enable (in the MSR) 360a47a12beSStefan Roese * and checkstop reset enable (in the reset mode register) are 361a47a12beSStefan Roese * turned off and so a checkstop condition will result in the cpu 362a47a12beSStefan Roese * halting. 363a47a12beSStefan Roese * 364a47a12beSStefan Roese * I force the cpu into a checkstop condition by putting an illegal 365a47a12beSStefan Roese * instruction here (at least this is the theory). 366a47a12beSStefan Roese * 367a47a12beSStefan Roese * well - that didnt work, so just do an infinite loop! 368a47a12beSStefan Roese */ 369a47a12beSStefan Roese1: b 1b 370a47a12beSStefan Roese#else 371a47a12beSStefan Roese STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 372a47a12beSStefan Roese#endif 373a47a12beSStefan Roese STD_EXCEPTION(0x1400, SMI, UnknownException) 374a47a12beSStefan Roese 375a47a12beSStefan Roese STD_EXCEPTION(0x1500, Trap_15, UnknownException) 376a47a12beSStefan Roese STD_EXCEPTION(0x1600, Trap_16, UnknownException) 377a47a12beSStefan Roese STD_EXCEPTION(0x1700, Trap_17, UnknownException) 378a47a12beSStefan Roese STD_EXCEPTION(0x1800, Trap_18, UnknownException) 379a47a12beSStefan Roese STD_EXCEPTION(0x1900, Trap_19, UnknownException) 380a47a12beSStefan Roese STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 381a47a12beSStefan Roese STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 382a47a12beSStefan Roese STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 383a47a12beSStefan Roese STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 384a47a12beSStefan Roese STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 385a47a12beSStefan Roese STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 386a47a12beSStefan Roese STD_EXCEPTION(0x2000, Trap_20, UnknownException) 387a47a12beSStefan Roese STD_EXCEPTION(0x2100, Trap_21, UnknownException) 388a47a12beSStefan Roese STD_EXCEPTION(0x2200, Trap_22, UnknownException) 389a47a12beSStefan Roese STD_EXCEPTION(0x2300, Trap_23, UnknownException) 390a47a12beSStefan Roese STD_EXCEPTION(0x2400, Trap_24, UnknownException) 391a47a12beSStefan Roese STD_EXCEPTION(0x2500, Trap_25, UnknownException) 392a47a12beSStefan Roese STD_EXCEPTION(0x2600, Trap_26, UnknownException) 393a47a12beSStefan Roese STD_EXCEPTION(0x2700, Trap_27, UnknownException) 394a47a12beSStefan Roese STD_EXCEPTION(0x2800, Trap_28, UnknownException) 395a47a12beSStefan Roese STD_EXCEPTION(0x2900, Trap_29, UnknownException) 396a47a12beSStefan Roese STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 397a47a12beSStefan Roese STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 398a47a12beSStefan Roese STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 399a47a12beSStefan Roese STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 400a47a12beSStefan Roese STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 401a47a12beSStefan Roese STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 402a47a12beSStefan Roese 403a47a12beSStefan Roese 404a47a12beSStefan Roese .globl _end_of_vectors 405a47a12beSStefan Roese_end_of_vectors: 406a47a12beSStefan Roese 407a47a12beSStefan Roese . = 0x3000 408a47a12beSStefan Roese 409a47a12beSStefan Roese/* 410a47a12beSStefan Roese * This code finishes saving the registers to the exception frame 411a47a12beSStefan Roese * and jumps to the appropriate handler for the exception. 412a47a12beSStefan Roese * Register r21 is pointer into trap frame, r1 has new stack pointer. 413a47a12beSStefan Roese */ 414a47a12beSStefan Roese .globl transfer_to_handler 415a47a12beSStefan Roesetransfer_to_handler: 416a47a12beSStefan Roese stw r22,_NIP(r21) 417a47a12beSStefan Roese lis r22,MSR_POW@h 418a47a12beSStefan Roese andc r23,r23,r22 419a47a12beSStefan Roese stw r23,_MSR(r21) 420a47a12beSStefan Roese SAVE_GPR(7, r21) 421a47a12beSStefan Roese SAVE_4GPRS(8, r21) 422a47a12beSStefan Roese SAVE_8GPRS(12, r21) 423a47a12beSStefan Roese SAVE_8GPRS(24, r21) 424a47a12beSStefan Roese mflr r23 425a47a12beSStefan Roese andi. r24,r23,0x3f00 /* get vector offset */ 426a47a12beSStefan Roese stw r24,TRAP(r21) 427a47a12beSStefan Roese li r22,0 428a47a12beSStefan Roese stw r22,RESULT(r21) 429a47a12beSStefan Roese lwz r24,0(r23) /* virtual address of handler */ 430a47a12beSStefan Roese lwz r23,4(r23) /* where to go when done */ 431a47a12beSStefan Roese mtspr SRR0,r24 432a47a12beSStefan Roese mtspr SRR1,r20 433a47a12beSStefan Roese mtlr r23 434a47a12beSStefan Roese SYNC 435a47a12beSStefan Roese rfi /* jump to handler, enable MMU */ 436a47a12beSStefan Roese 437a47a12beSStefan Roeseint_return: 438a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 439a47a12beSStefan Roese li r4,0 440a47a12beSStefan Roese ori r4,r4,MSR_EE 441a47a12beSStefan Roese andc r28,r28,r4 442a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 443a47a12beSStefan Roese mtmsr r28 444a47a12beSStefan Roese SYNC 445a47a12beSStefan Roese lwz r2,_CTR(r1) 446a47a12beSStefan Roese lwz r0,_LINK(r1) 447a47a12beSStefan Roese mtctr r2 448a47a12beSStefan Roese mtlr r0 449a47a12beSStefan Roese lwz r2,_XER(r1) 450a47a12beSStefan Roese lwz r0,_CCR(r1) 451a47a12beSStefan Roese mtspr XER,r2 452a47a12beSStefan Roese mtcrf 0xFF,r0 453a47a12beSStefan Roese REST_10GPRS(3, r1) 454a47a12beSStefan Roese REST_10GPRS(13, r1) 455a47a12beSStefan Roese REST_8GPRS(23, r1) 456a47a12beSStefan Roese REST_GPR(31, r1) 457a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 458a47a12beSStefan Roese lwz r0,_MSR(r1) 459a47a12beSStefan Roese mtspr SRR0,r2 460a47a12beSStefan Roese mtspr SRR1,r0 461a47a12beSStefan Roese lwz r0,GPR0(r1) 462a47a12beSStefan Roese lwz r2,GPR2(r1) 463a47a12beSStefan Roese lwz r1,GPR1(r1) 464a47a12beSStefan Roese SYNC 465a47a12beSStefan Roese rfi 46606f60ae3SScott Wood#endif /* !MINIMAL_SPL */ 467a47a12beSStefan Roese 468a47a12beSStefan Roese/* 469a47a12beSStefan Roese * This code initialises the E300 processor core 470a47a12beSStefan Roese * (conforms to PowerPC 603e spec) 471a47a12beSStefan Roese * Note: expects original MSR contents to be in r5. 472a47a12beSStefan Roese */ 473a47a12beSStefan Roese .globl init_e300_core 474a47a12beSStefan Roeseinit_e300_core: /* time t 10 */ 475a47a12beSStefan Roese /* Initialize machine status; enable machine check interrupt */ 476a47a12beSStefan Roese /*-----------------------------------------------------------*/ 477a47a12beSStefan Roese 478a47a12beSStefan Roese li r3, MSR_KERNEL /* Set ME and RI flags */ 479a47a12beSStefan Roese rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 480a47a12beSStefan Roese#ifdef DEBUG 481a47a12beSStefan Roese rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 482a47a12beSStefan Roese#endif 483a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 484a47a12beSStefan Roese mtmsr r3 485a47a12beSStefan Roese SYNC 486a47a12beSStefan Roese mtspr SRR1, r3 /* Make SRR1 match MSR */ 487a47a12beSStefan Roese 488a47a12beSStefan Roese 489a47a12beSStefan Roese lis r3, CONFIG_SYS_IMMR@h 490a47a12beSStefan Roese#if defined(CONFIG_WATCHDOG) 491f6970d0cSHorst Kronstorfer /* Initialise the Watchdog values and reset it (if req) */ 492a47a12beSStefan Roese /*------------------------------------------------------*/ 493a47a12beSStefan Roese lis r4, CONFIG_SYS_WATCHDOG_VALUE 494a47a12beSStefan Roese ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 495a47a12beSStefan Roese stw r4, SWCRR(r3) 496a47a12beSStefan Roese 497a47a12beSStefan Roese /* and reset it */ 498a47a12beSStefan Roese 499a47a12beSStefan Roese li r4, 0x556C 500a47a12beSStefan Roese sth r4, SWSRR@l(r3) 501a47a12beSStefan Roese li r4, -0x55C7 502a47a12beSStefan Roese sth r4, SWSRR@l(r3) 503a47a12beSStefan Roese#else 504f6970d0cSHorst Kronstorfer /* Disable Watchdog */ 505a47a12beSStefan Roese /*-------------------*/ 506a47a12beSStefan Roese lwz r4, SWCRR(r3) 507a47a12beSStefan Roese /* Check to see if its enabled for disabling 508a47a12beSStefan Roese once disabled by SW you can't re-enable */ 509a47a12beSStefan Roese andi. r4, r4, 0x4 510a47a12beSStefan Roese beq 1f 511a47a12beSStefan Roese xor r4, r4, r4 512a47a12beSStefan Roese stw r4, SWCRR(r3) 513a47a12beSStefan Roese1: 514a47a12beSStefan Roese#endif /* CONFIG_WATCHDOG */ 515a47a12beSStefan Roese 516a47a12beSStefan Roese#if defined(CONFIG_MASK_AER_AO) 517a47a12beSStefan Roese /* Write the Arbiter Event Enable to mask Address Only traps. */ 518a47a12beSStefan Roese /* This prevents the dcbz instruction from being trapped when */ 519a47a12beSStefan Roese /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 520a47a12beSStefan Roese /* COHERENCY bit is set in the WIMG bits, which is often */ 521a47a12beSStefan Roese /* needed for PCI operation. */ 522a47a12beSStefan Roese lwz r4, 0x0808(r3) 523a47a12beSStefan Roese rlwinm r0, r4, 0, ~AER_AO 524a47a12beSStefan Roese stw r0, 0x0808(r3) 525a47a12beSStefan Roese#endif /* CONFIG_MASK_AER_AO */ 526a47a12beSStefan Roese 527a47a12beSStefan Roese /* Initialize the Hardware Implementation-dependent Registers */ 528a47a12beSStefan Roese /* HID0 also contains cache control */ 529a47a12beSStefan Roese /* - force invalidation of data and instruction caches */ 530a47a12beSStefan Roese /*------------------------------------------------------*/ 531a47a12beSStefan Roese 532a47a12beSStefan Roese lis r3, CONFIG_SYS_HID0_INIT@h 533a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 534a47a12beSStefan Roese SYNC 535a47a12beSStefan Roese mtspr HID0, r3 536a47a12beSStefan Roese 537a47a12beSStefan Roese lis r3, CONFIG_SYS_HID0_FINAL@h 538a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 539a47a12beSStefan Roese SYNC 540a47a12beSStefan Roese mtspr HID0, r3 541a47a12beSStefan Roese 542a47a12beSStefan Roese lis r3, CONFIG_SYS_HID2@h 543a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_HID2@l 544a47a12beSStefan Roese SYNC 545a47a12beSStefan Roese mtspr HID2, r3 546a47a12beSStefan Roese 547a47a12beSStefan Roese /* Done! */ 548a47a12beSStefan Roese /*------------------------------*/ 549a47a12beSStefan Roese blr 550a47a12beSStefan Roese 551a47a12beSStefan Roese /* setup_bats - set them up to some initial state */ 552a47a12beSStefan Roese .globl setup_bats 553a47a12beSStefan Roesesetup_bats: 554a47a12beSStefan Roese addis r0, r0, 0x0000 555a47a12beSStefan Roese 556a47a12beSStefan Roese /* IBAT 0 */ 557a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_IBAT0L@h 558a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT0L@l 559a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_IBAT0U@h 560a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT0U@l 561a47a12beSStefan Roese mtspr IBAT0L, r4 562a47a12beSStefan Roese mtspr IBAT0U, r3 563a47a12beSStefan Roese 564a47a12beSStefan Roese /* DBAT 0 */ 565a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_DBAT0L@h 566a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT0L@l 567a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_DBAT0U@h 568a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT0U@l 569a47a12beSStefan Roese mtspr DBAT0L, r4 570a47a12beSStefan Roese mtspr DBAT0U, r3 571a47a12beSStefan Roese 572a47a12beSStefan Roese /* IBAT 1 */ 573a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_IBAT1L@h 574a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT1L@l 575a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_IBAT1U@h 576a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT1U@l 577a47a12beSStefan Roese mtspr IBAT1L, r4 578a47a12beSStefan Roese mtspr IBAT1U, r3 579a47a12beSStefan Roese 580a47a12beSStefan Roese /* DBAT 1 */ 581a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_DBAT1L@h 582a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT1L@l 583a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_DBAT1U@h 584a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT1U@l 585a47a12beSStefan Roese mtspr DBAT1L, r4 586a47a12beSStefan Roese mtspr DBAT1U, r3 587a47a12beSStefan Roese 588a47a12beSStefan Roese /* IBAT 2 */ 589a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_IBAT2L@h 590a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT2L@l 591a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_IBAT2U@h 592a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT2U@l 593a47a12beSStefan Roese mtspr IBAT2L, r4 594a47a12beSStefan Roese mtspr IBAT2U, r3 595a47a12beSStefan Roese 596a47a12beSStefan Roese /* DBAT 2 */ 597a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_DBAT2L@h 598a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT2L@l 599a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_DBAT2U@h 600a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT2U@l 601a47a12beSStefan Roese mtspr DBAT2L, r4 602a47a12beSStefan Roese mtspr DBAT2U, r3 603a47a12beSStefan Roese 604a47a12beSStefan Roese /* IBAT 3 */ 605a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_IBAT3L@h 606a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT3L@l 607a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_IBAT3U@h 608a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT3U@l 609a47a12beSStefan Roese mtspr IBAT3L, r4 610a47a12beSStefan Roese mtspr IBAT3U, r3 611a47a12beSStefan Roese 612a47a12beSStefan Roese /* DBAT 3 */ 613a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_DBAT3L@h 614a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT3L@l 615a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_DBAT3U@h 616a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT3U@l 617a47a12beSStefan Roese mtspr DBAT3L, r4 618a47a12beSStefan Roese mtspr DBAT3U, r3 619a47a12beSStefan Roese 620a47a12beSStefan Roese#ifdef CONFIG_HIGH_BATS 621a47a12beSStefan Roese /* IBAT 4 */ 622a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_IBAT4L@h 623a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT4L@l 624a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_IBAT4U@h 625a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT4U@l 626a47a12beSStefan Roese mtspr IBAT4L, r4 627a47a12beSStefan Roese mtspr IBAT4U, r3 628a47a12beSStefan Roese 629a47a12beSStefan Roese /* DBAT 4 */ 630a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_DBAT4L@h 631a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT4L@l 632a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_DBAT4U@h 633a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT4U@l 634a47a12beSStefan Roese mtspr DBAT4L, r4 635a47a12beSStefan Roese mtspr DBAT4U, r3 636a47a12beSStefan Roese 637a47a12beSStefan Roese /* IBAT 5 */ 638a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_IBAT5L@h 639a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT5L@l 640a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_IBAT5U@h 641a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT5U@l 642a47a12beSStefan Roese mtspr IBAT5L, r4 643a47a12beSStefan Roese mtspr IBAT5U, r3 644a47a12beSStefan Roese 645a47a12beSStefan Roese /* DBAT 5 */ 646a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_DBAT5L@h 647a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT5L@l 648a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_DBAT5U@h 649a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT5U@l 650a47a12beSStefan Roese mtspr DBAT5L, r4 651a47a12beSStefan Roese mtspr DBAT5U, r3 652a47a12beSStefan Roese 653a47a12beSStefan Roese /* IBAT 6 */ 654a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_IBAT6L@h 655a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT6L@l 656a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_IBAT6U@h 657a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT6U@l 658a47a12beSStefan Roese mtspr IBAT6L, r4 659a47a12beSStefan Roese mtspr IBAT6U, r3 660a47a12beSStefan Roese 661a47a12beSStefan Roese /* DBAT 6 */ 662a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_DBAT6L@h 663a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT6L@l 664a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_DBAT6U@h 665a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT6U@l 666a47a12beSStefan Roese mtspr DBAT6L, r4 667a47a12beSStefan Roese mtspr DBAT6U, r3 668a47a12beSStefan Roese 669a47a12beSStefan Roese /* IBAT 7 */ 670a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_IBAT7L@h 671a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT7L@l 672a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_IBAT7U@h 673a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT7U@l 674a47a12beSStefan Roese mtspr IBAT7L, r4 675a47a12beSStefan Roese mtspr IBAT7U, r3 676a47a12beSStefan Roese 677a47a12beSStefan Roese /* DBAT 7 */ 678a47a12beSStefan Roese addis r4, r0, CONFIG_SYS_DBAT7L@h 679a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT7L@l 680a47a12beSStefan Roese addis r3, r0, CONFIG_SYS_DBAT7U@h 681a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT7U@l 682a47a12beSStefan Roese mtspr DBAT7L, r4 683a47a12beSStefan Roese mtspr DBAT7U, r3 684a47a12beSStefan Roese#endif 685a47a12beSStefan Roese 686a47a12beSStefan Roese isync 687a47a12beSStefan Roese 688a47a12beSStefan Roese /* invalidate all tlb's 689a47a12beSStefan Roese * 690a47a12beSStefan Roese * From the 603e User Manual: "The 603e provides the ability to 691a47a12beSStefan Roese * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 692a47a12beSStefan Roese * instruction invalidates the TLB entry indexed by the EA, and 693a47a12beSStefan Roese * operates on both the instruction and data TLBs simultaneously 694a47a12beSStefan Roese * invalidating four TLB entries (both sets in each TLB). The 695a47a12beSStefan Roese * index corresponds to bits 15-19 of the EA. To invalidate all 696a47a12beSStefan Roese * entries within both TLBs, 32 tlbie instructions should be 697a47a12beSStefan Roese * issued, incrementing this field by one each time." 698a47a12beSStefan Roese * 699a47a12beSStefan Roese * "Note that the tlbia instruction is not implemented on the 700a47a12beSStefan Roese * 603e." 701a47a12beSStefan Roese * 702a47a12beSStefan Roese * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 703a47a12beSStefan Roese * incrementing by 0x1000 each time. The code below is sort of 704a47a12beSStefan Roese * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 705a47a12beSStefan Roese * 706a47a12beSStefan Roese */ 707a47a12beSStefan Roese lis r3, 0 708a47a12beSStefan Roese lis r5, 2 709a47a12beSStefan Roese 710a47a12beSStefan Roese1: 711a47a12beSStefan Roese tlbie r3 712a47a12beSStefan Roese addi r3, r3, 0x1000 713a47a12beSStefan Roese cmp 0, 0, r3, r5 714a47a12beSStefan Roese blt 1b 715a47a12beSStefan Roese 716a47a12beSStefan Roese blr 717a47a12beSStefan Roese 718a47a12beSStefan Roese/* Cache functions. 719a47a12beSStefan Roese * 720a47a12beSStefan Roese * Note: requires that all cache bits in 721a47a12beSStefan Roese * HID0 are in the low half word. 722a47a12beSStefan Roese */ 72306f60ae3SScott Wood#ifndef MINIMAL_SPL 724a47a12beSStefan Roese .globl icache_enable 725a47a12beSStefan Roeseicache_enable: 726a47a12beSStefan Roese mfspr r3, HID0 727a47a12beSStefan Roese ori r3, r3, HID0_ICE 728a47a12beSStefan Roese li r4, HID0_ICFI|HID0_ILOCK 729a47a12beSStefan Roese andc r3, r3, r4 730a47a12beSStefan Roese ori r4, r3, HID0_ICFI 731a47a12beSStefan Roese isync 732a47a12beSStefan Roese mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 733a47a12beSStefan Roese isync 734a47a12beSStefan Roese mtspr HID0, r3 /* clears invalidate */ 735a47a12beSStefan Roese blr 736a47a12beSStefan Roese 737a47a12beSStefan Roese .globl icache_disable 738a47a12beSStefan Roeseicache_disable: 739a47a12beSStefan Roese mfspr r3, HID0 740a47a12beSStefan Roese lis r4, 0 741a47a12beSStefan Roese ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 742a47a12beSStefan Roese andc r3, r3, r4 743a47a12beSStefan Roese isync 744a47a12beSStefan Roese mtspr HID0, r3 /* clears invalidate, enable and lock */ 745a47a12beSStefan Roese blr 746a47a12beSStefan Roese 747a47a12beSStefan Roese .globl icache_status 748a47a12beSStefan Roeseicache_status: 749a47a12beSStefan Roese mfspr r3, HID0 750a47a12beSStefan Roese rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 751a47a12beSStefan Roese blr 75206f60ae3SScott Wood#endif /* !MINIMAL_SPL */ 753a47a12beSStefan Roese 754a47a12beSStefan Roese .globl dcache_enable 755a47a12beSStefan Roesedcache_enable: 756a47a12beSStefan Roese mfspr r3, HID0 757a47a12beSStefan Roese li r5, HID0_DCFI|HID0_DLOCK 758a47a12beSStefan Roese andc r3, r3, r5 759a47a12beSStefan Roese ori r3, r3, HID0_DCE 760a47a12beSStefan Roese sync 761a47a12beSStefan Roese mtspr HID0, r3 /* enable, no invalidate */ 762a47a12beSStefan Roese blr 763a47a12beSStefan Roese 764a47a12beSStefan Roese .globl dcache_disable 765a47a12beSStefan Roesedcache_disable: 766a47a12beSStefan Roese mflr r4 767a47a12beSStefan Roese bl flush_dcache /* uses r3 and r5 */ 768a47a12beSStefan Roese mfspr r3, HID0 769a47a12beSStefan Roese li r5, HID0_DCE|HID0_DLOCK 770a47a12beSStefan Roese andc r3, r3, r5 771a47a12beSStefan Roese ori r5, r3, HID0_DCFI 772a47a12beSStefan Roese sync 773a47a12beSStefan Roese mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 774a47a12beSStefan Roese sync 775a47a12beSStefan Roese mtspr HID0, r3 /* clears invalidate */ 776a47a12beSStefan Roese mtlr r4 777a47a12beSStefan Roese blr 778a47a12beSStefan Roese 779a47a12beSStefan Roese .globl dcache_status 780a47a12beSStefan Roesedcache_status: 781a47a12beSStefan Roese mfspr r3, HID0 782a47a12beSStefan Roese rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 783a47a12beSStefan Roese blr 784a47a12beSStefan Roese 785a47a12beSStefan Roese .globl flush_dcache 786a47a12beSStefan Roeseflush_dcache: 787a47a12beSStefan Roese lis r3, 0 788a47a12beSStefan Roese lis r5, CONFIG_SYS_CACHELINE_SIZE 789a47a12beSStefan Roese1: cmp 0, 1, r3, r5 790a47a12beSStefan Roese bge 2f 791a47a12beSStefan Roese lwz r5, 0(r3) 792a47a12beSStefan Roese lis r5, CONFIG_SYS_CACHELINE_SIZE 793a47a12beSStefan Roese addi r3, r3, 0x4 794a47a12beSStefan Roese b 1b 795a47a12beSStefan Roese2: blr 796a47a12beSStefan Roese 797a47a12beSStefan Roese/*-------------------------------------------------------------------*/ 798a47a12beSStefan Roese 799a47a12beSStefan Roese/* 800a47a12beSStefan Roese * void relocate_code (addr_sp, gd, addr_moni) 801a47a12beSStefan Roese * 802a47a12beSStefan Roese * This "function" does not return, instead it continues in RAM 803a47a12beSStefan Roese * after relocating the monitor code. 804a47a12beSStefan Roese * 805a47a12beSStefan Roese * r3 = dest 806a47a12beSStefan Roese * r4 = src 807a47a12beSStefan Roese * r5 = length in bytes 808a47a12beSStefan Roese * r6 = cachelinesize 809a47a12beSStefan Roese */ 810a47a12beSStefan Roese .globl relocate_code 811a47a12beSStefan Roeserelocate_code: 812a47a12beSStefan Roese mr r1, r3 /* Set new stack pointer */ 813a47a12beSStefan Roese mr r9, r4 /* Save copy of Global Data pointer */ 814a47a12beSStefan Roese mr r10, r5 /* Save copy of Destination Address */ 815a47a12beSStefan Roese 816a47a12beSStefan Roese GET_GOT 817a47a12beSStefan Roese mr r3, r5 /* Destination Address */ 818a47a12beSStefan Roese lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 819a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 820a47a12beSStefan Roese lwz r5, GOT(__bss_start) 821a47a12beSStefan Roese sub r5, r5, r4 822a47a12beSStefan Roese li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 823a47a12beSStefan Roese 824a47a12beSStefan Roese /* 825a47a12beSStefan Roese * Fix GOT pointer: 826a47a12beSStefan Roese * 827a47a12beSStefan Roese * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 828a47a12beSStefan Roese * + Destination Address 829a47a12beSStefan Roese * 830a47a12beSStefan Roese * Offset: 831a47a12beSStefan Roese */ 832a47a12beSStefan Roese sub r15, r10, r4 833a47a12beSStefan Roese 834a47a12beSStefan Roese /* First our own GOT */ 835a47a12beSStefan Roese add r12, r12, r15 836a47a12beSStefan Roese /* then the one used by the C code */ 837a47a12beSStefan Roese add r30, r30, r15 838a47a12beSStefan Roese 839a47a12beSStefan Roese /* 840a47a12beSStefan Roese * Now relocate code 841a47a12beSStefan Roese */ 842a47a12beSStefan Roese 843a47a12beSStefan Roese cmplw cr1,r3,r4 844a47a12beSStefan Roese addi r0,r5,3 845a47a12beSStefan Roese srwi. r0,r0,2 846a47a12beSStefan Roese beq cr1,4f /* In place copy is not necessary */ 847a47a12beSStefan Roese beq 7f /* Protect against 0 count */ 848a47a12beSStefan Roese mtctr r0 849a47a12beSStefan Roese bge cr1,2f 850a47a12beSStefan Roese la r8,-4(r4) 851a47a12beSStefan Roese la r7,-4(r3) 852a47a12beSStefan Roese 853a47a12beSStefan Roese /* copy */ 854a47a12beSStefan Roese1: lwzu r0,4(r8) 855a47a12beSStefan Roese stwu r0,4(r7) 856a47a12beSStefan Roese bdnz 1b 857a47a12beSStefan Roese 858a47a12beSStefan Roese addi r0,r5,3 859a47a12beSStefan Roese srwi. r0,r0,2 860a47a12beSStefan Roese mtctr r0 861a47a12beSStefan Roese la r8,-4(r4) 862a47a12beSStefan Roese la r7,-4(r3) 863a47a12beSStefan Roese 864a47a12beSStefan Roese /* and compare */ 865a47a12beSStefan Roese20: lwzu r20,4(r8) 866a47a12beSStefan Roese lwzu r21,4(r7) 867a47a12beSStefan Roese xor. r22, r20, r21 868a47a12beSStefan Roese bne 30f 869a47a12beSStefan Roese bdnz 20b 870a47a12beSStefan Roese b 4f 871a47a12beSStefan Roese 872a47a12beSStefan Roese /* compare failed */ 873a47a12beSStefan Roese30: li r3, 0 874a47a12beSStefan Roese blr 875a47a12beSStefan Roese 876a47a12beSStefan Roese2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 877a47a12beSStefan Roese add r8,r4,r0 878a47a12beSStefan Roese add r7,r3,r0 879a47a12beSStefan Roese3: lwzu r0,-4(r8) 880a47a12beSStefan Roese stwu r0,-4(r7) 881a47a12beSStefan Roese bdnz 3b 882a47a12beSStefan Roese 883a47a12beSStefan Roese/* 884a47a12beSStefan Roese * Now flush the cache: note that we must start from a cache aligned 885a47a12beSStefan Roese * address. Otherwise we might miss one cache line. 886a47a12beSStefan Roese */ 887a47a12beSStefan Roese4: cmpwi r6,0 888a47a12beSStefan Roese add r5,r3,r5 889a47a12beSStefan Roese beq 7f /* Always flush prefetch queue in any case */ 890a47a12beSStefan Roese subi r0,r6,1 891a47a12beSStefan Roese andc r3,r3,r0 892a47a12beSStefan Roese mr r4,r3 893a47a12beSStefan Roese5: dcbst 0,r4 894a47a12beSStefan Roese add r4,r4,r6 895a47a12beSStefan Roese cmplw r4,r5 896a47a12beSStefan Roese blt 5b 897a47a12beSStefan Roese sync /* Wait for all dcbst to complete on bus */ 898a47a12beSStefan Roese mr r4,r3 899a47a12beSStefan Roese6: icbi 0,r4 900a47a12beSStefan Roese add r4,r4,r6 901a47a12beSStefan Roese cmplw r4,r5 902a47a12beSStefan Roese blt 6b 903a47a12beSStefan Roese7: sync /* Wait for all icbi to complete on bus */ 904a47a12beSStefan Roese isync 905a47a12beSStefan Roese 906a47a12beSStefan Roese/* 907a47a12beSStefan Roese * We are done. Do not return, instead branch to second part of board 908a47a12beSStefan Roese * initialization, now running from RAM. 909a47a12beSStefan Roese */ 910a47a12beSStefan Roese addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 911a47a12beSStefan Roese mtlr r0 912a47a12beSStefan Roese blr 913a47a12beSStefan Roese 914a47a12beSStefan Roesein_ram: 915a47a12beSStefan Roese 916a47a12beSStefan Roese /* 917a47a12beSStefan Roese * Relocation Function, r12 point to got2+0x8000 918a47a12beSStefan Roese * 919a47a12beSStefan Roese * Adjust got2 pointers, no need to check for 0, this code 920a47a12beSStefan Roese * already puts a few entries in the table. 921a47a12beSStefan Roese */ 922a47a12beSStefan Roese li r0,__got2_entries@sectoff@l 923a47a12beSStefan Roese la r3,GOT(_GOT2_TABLE_) 924a47a12beSStefan Roese lwz r11,GOT(_GOT2_TABLE_) 925a47a12beSStefan Roese mtctr r0 926a47a12beSStefan Roese sub r11,r3,r11 927a47a12beSStefan Roese addi r3,r3,-4 928a47a12beSStefan Roese1: lwzu r0,4(r3) 929a47a12beSStefan Roese cmpwi r0,0 930a47a12beSStefan Roese beq- 2f 931a47a12beSStefan Roese add r0,r0,r11 932a47a12beSStefan Roese stw r0,0(r3) 933a47a12beSStefan Roese2: bdnz 1b 934a47a12beSStefan Roese 93506f60ae3SScott Wood#ifndef MINIMAL_SPL 936a47a12beSStefan Roese /* 937a47a12beSStefan Roese * Now adjust the fixups and the pointers to the fixups 938a47a12beSStefan Roese * in case we need to move ourselves again. 939a47a12beSStefan Roese */ 940a47a12beSStefan Roese li r0,__fixup_entries@sectoff@l 941a47a12beSStefan Roese lwz r3,GOT(_FIXUP_TABLE_) 942a47a12beSStefan Roese cmpwi r0,0 943a47a12beSStefan Roese mtctr r0 944a47a12beSStefan Roese addi r3,r3,-4 945a47a12beSStefan Roese beq 4f 946a47a12beSStefan Roese3: lwzu r4,4(r3) 947a47a12beSStefan Roese lwzux r0,r4,r11 948d1e0b10aSJoakim Tjernlund cmpwi r0,0 949a47a12beSStefan Roese add r0,r0,r11 95034bbf618SJoakim Tjernlund stw r4,0(r3) 951d1e0b10aSJoakim Tjernlund beq- 5f 952a47a12beSStefan Roese stw r0,0(r4) 953d1e0b10aSJoakim Tjernlund5: bdnz 3b 954a47a12beSStefan Roese4: 955a47a12beSStefan Roese#endif 956a47a12beSStefan Roese 957a47a12beSStefan Roeseclear_bss: 958a47a12beSStefan Roese /* 959a47a12beSStefan Roese * Now clear BSS segment 960a47a12beSStefan Roese */ 961a47a12beSStefan Roese lwz r3,GOT(__bss_start) 962a47a12beSStefan Roese#if defined(CONFIG_HYMOD) 963a47a12beSStefan Roese /* 964a47a12beSStefan Roese * For HYMOD - the environment is the very last item in flash. 965a47a12beSStefan Roese * The real .bss stops just before environment starts, so only 966a47a12beSStefan Roese * clear up to that point. 967a47a12beSStefan Roese * 968a47a12beSStefan Roese * taken from mods for FADS board 969a47a12beSStefan Roese */ 970a47a12beSStefan Roese lwz r4,GOT(environment) 971a47a12beSStefan Roese#else 9723929fb0aSSimon Glass lwz r4,GOT(__bss_end) 973a47a12beSStefan Roese#endif 974a47a12beSStefan Roese 975a47a12beSStefan Roese cmplw 0, r3, r4 976a47a12beSStefan Roese beq 6f 977a47a12beSStefan Roese 978a47a12beSStefan Roese li r0, 0 979a47a12beSStefan Roese5: 980a47a12beSStefan Roese stw r0, 0(r3) 981a47a12beSStefan Roese addi r3, r3, 4 982a47a12beSStefan Roese cmplw 0, r3, r4 983a47a12beSStefan Roese bne 5b 984a47a12beSStefan Roese6: 985a47a12beSStefan Roese 986a47a12beSStefan Roese mr r3, r9 /* Global Data pointer */ 987a47a12beSStefan Roese mr r4, r10 /* Destination Address */ 988a47a12beSStefan Roese bl board_init_r 989a47a12beSStefan Roese 99006f60ae3SScott Wood#ifndef MINIMAL_SPL 991a47a12beSStefan Roese /* 992a47a12beSStefan Roese * Copy exception vector code to low memory 993a47a12beSStefan Roese * 994a47a12beSStefan Roese * r3: dest_addr 995a47a12beSStefan Roese * r7: source address, r8: end address, r9: target address 996a47a12beSStefan Roese */ 997a47a12beSStefan Roese .globl trap_init 998a47a12beSStefan Roesetrap_init: 999a47a12beSStefan Roese mflr r4 /* save link register */ 1000a47a12beSStefan Roese GET_GOT 1001a47a12beSStefan Roese lwz r7, GOT(_start) 1002a47a12beSStefan Roese lwz r8, GOT(_end_of_vectors) 1003a47a12beSStefan Roese 1004a47a12beSStefan Roese li r9, 0x100 /* reset vector always at 0x100 */ 1005a47a12beSStefan Roese 1006a47a12beSStefan Roese cmplw 0, r7, r8 1007a47a12beSStefan Roese bgelr /* return if r7>=r8 - just in case */ 1008a47a12beSStefan Roese1: 1009a47a12beSStefan Roese lwz r0, 0(r7) 1010a47a12beSStefan Roese stw r0, 0(r9) 1011a47a12beSStefan Roese addi r7, r7, 4 1012a47a12beSStefan Roese addi r9, r9, 4 1013a47a12beSStefan Roese cmplw 0, r7, r8 1014a47a12beSStefan Roese bne 1b 1015a47a12beSStefan Roese 1016a47a12beSStefan Roese /* 1017a47a12beSStefan Roese * relocate `hdlr' and `int_return' entries 1018a47a12beSStefan Roese */ 1019a47a12beSStefan Roese li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1020a47a12beSStefan Roese li r8, Alignment - _start + EXC_OFF_SYS_RESET 1021a47a12beSStefan Roese2: 1022a47a12beSStefan Roese bl trap_reloc 1023a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 1024a47a12beSStefan Roese cmplw 0, r7, r8 1025a47a12beSStefan Roese blt 2b 1026a47a12beSStefan Roese 1027a47a12beSStefan Roese li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1028a47a12beSStefan Roese bl trap_reloc 1029a47a12beSStefan Roese 1030a47a12beSStefan Roese li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1031a47a12beSStefan Roese bl trap_reloc 1032a47a12beSStefan Roese 1033a47a12beSStefan Roese li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1034a47a12beSStefan Roese li r8, SystemCall - _start + EXC_OFF_SYS_RESET 1035a47a12beSStefan Roese3: 1036a47a12beSStefan Roese bl trap_reloc 1037a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 1038a47a12beSStefan Roese cmplw 0, r7, r8 1039a47a12beSStefan Roese blt 3b 1040a47a12beSStefan Roese 1041a47a12beSStefan Roese li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1042a47a12beSStefan Roese li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 1043a47a12beSStefan Roese4: 1044a47a12beSStefan Roese bl trap_reloc 1045a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 1046a47a12beSStefan Roese cmplw 0, r7, r8 1047a47a12beSStefan Roese blt 4b 1048a47a12beSStefan Roese 1049a47a12beSStefan Roese mfmsr r3 /* now that the vectors have */ 1050a47a12beSStefan Roese lis r7, MSR_IP@h /* relocated into low memory */ 1051a47a12beSStefan Roese ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1052a47a12beSStefan Roese andc r3, r3, r7 /* (if it was on) */ 1053a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 1054a47a12beSStefan Roese mtmsr r3 1055a47a12beSStefan Roese SYNC 1056a47a12beSStefan Roese 1057a47a12beSStefan Roese mtlr r4 /* restore link register */ 1058a47a12beSStefan Roese blr 1059a47a12beSStefan Roese 106006f60ae3SScott Wood#endif /* !MINIMAL_SPL */ 1061a47a12beSStefan Roese 1062a47a12beSStefan Roese#ifdef CONFIG_SYS_INIT_RAM_LOCK 1063a47a12beSStefan Roeselock_ram_in_cache: 1064a47a12beSStefan Roese /* Allocate Initial RAM in data cache. 1065a47a12beSStefan Roese */ 1066a47a12beSStefan Roese lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1067a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1068553f0982SWolfgang Denk li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1069a47a12beSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1070a47a12beSStefan Roese mtctr r4 1071a47a12beSStefan Roese1: 1072a47a12beSStefan Roese dcbz r0, r3 1073a47a12beSStefan Roese addi r3, r3, 32 1074a47a12beSStefan Roese bdnz 1b 1075a47a12beSStefan Roese 1076a47a12beSStefan Roese /* Lock the data cache */ 1077a47a12beSStefan Roese mfspr r0, HID0 1078a47a12beSStefan Roese ori r0, r0, HID0_DLOCK 1079a47a12beSStefan Roese sync 1080a47a12beSStefan Roese mtspr HID0, r0 1081a47a12beSStefan Roese sync 1082a47a12beSStefan Roese blr 1083a47a12beSStefan Roese 108406f60ae3SScott Wood#ifndef MINIMAL_SPL 1085a47a12beSStefan Roese.globl unlock_ram_in_cache 1086a47a12beSStefan Roeseunlock_ram_in_cache: 1087a47a12beSStefan Roese /* invalidate the INIT_RAM section */ 1088a47a12beSStefan Roese lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1089a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1090553f0982SWolfgang Denk li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1091a47a12beSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1092a47a12beSStefan Roese mtctr r4 1093a47a12beSStefan Roese1: icbi r0, r3 1094a47a12beSStefan Roese dcbi r0, r3 1095a47a12beSStefan Roese addi r3, r3, 32 1096a47a12beSStefan Roese bdnz 1b 1097a47a12beSStefan Roese sync /* Wait for all icbi to complete on bus */ 1098a47a12beSStefan Roese isync 1099a47a12beSStefan Roese 1100a47a12beSStefan Roese /* Unlock the data cache and invalidate it */ 1101a47a12beSStefan Roese mfspr r3, HID0 1102a47a12beSStefan Roese li r5, HID0_DLOCK|HID0_DCFI 1103a47a12beSStefan Roese andc r3, r3, r5 /* no invalidate, unlock */ 1104a47a12beSStefan Roese ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1105a47a12beSStefan Roese sync 1106a47a12beSStefan Roese mtspr HID0, r5 /* invalidate, unlock */ 1107a47a12beSStefan Roese sync 1108a47a12beSStefan Roese mtspr HID0, r3 /* no invalidate, unlock */ 1109a47a12beSStefan Roese blr 111006f60ae3SScott Wood#endif /* !MINIMAL_SPL */ 1111a47a12beSStefan Roese#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1112a47a12beSStefan Roese 1113a47a12beSStefan Roese#ifdef CONFIG_SYS_FLASHBOOT 1114a47a12beSStefan Roesemap_flash_by_law1: 1115a47a12beSStefan Roese /* When booting from ROM (Flash or EPROM), clear the */ 1116a47a12beSStefan Roese /* Address Mask in OR0 so ROM appears everywhere */ 1117a47a12beSStefan Roese /*----------------------------------------------------*/ 1118a47a12beSStefan Roese lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1119a47a12beSStefan Roese lwz r4, OR0@l(r3) 1120a47a12beSStefan Roese li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1121a47a12beSStefan Roese and r4, r4, r5 1122a47a12beSStefan Roese stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1123a47a12beSStefan Roese 1124a47a12beSStefan Roese /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1125a47a12beSStefan Roese * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1126a47a12beSStefan Roese * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1127a47a12beSStefan Roese * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1128a47a12beSStefan Roese * 0xFF800. From the hard resetting to here, the processor fetched and 1129a47a12beSStefan Roese * executed the instructions one by one. There is not absolutely 1130a47a12beSStefan Roese * jumping happened. Laterly, the u-boot code has to do an absolutely 1131a47a12beSStefan Roese * jumping to tell the CPU instruction fetching component what the 1132a47a12beSStefan Roese * u-boot TEXT base address is. Because the TEXT base resides in the 1133a47a12beSStefan Roese * boot ROM memory space, to garantee the code can run smoothly after 1134a47a12beSStefan Roese * that jumping, we must map in the entire boot ROM by Local Access 1135a47a12beSStefan Roese * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1136a47a12beSStefan Roese * address for boot ROM, such as 0xFE000000. In this case, the default 1137a47a12beSStefan Roese * LBIU Local Access Widow 0 will not cover this memory space. So, we 1138a47a12beSStefan Roese * need another window to map in it. 1139a47a12beSStefan Roese */ 1140a47a12beSStefan Roese lis r4, (CONFIG_SYS_FLASH_BASE)@h 1141a47a12beSStefan Roese ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1142a47a12beSStefan Roese stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1143a47a12beSStefan Roese 1144a47a12beSStefan Roese /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1145a47a12beSStefan Roese lis r4, (0x80000012)@h 1146a47a12beSStefan Roese ori r4, r4, (0x80000012)@l 1147a47a12beSStefan Roese li r5, CONFIG_SYS_FLASH_SIZE 1148a47a12beSStefan Roese1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1149a47a12beSStefan Roese addi r4, r4, 1 1150a47a12beSStefan Roese bne 1b 1151a47a12beSStefan Roese 1152a47a12beSStefan Roese stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1153e45c98adSJoakim Tjernlund /* Wait for HW to catch up */ 1154e45c98adSJoakim Tjernlund lwz r4, LBLAWAR1(r3) 1155e45c98adSJoakim Tjernlund twi 0,r4,0 1156e45c98adSJoakim Tjernlund isync 1157a47a12beSStefan Roese blr 1158a47a12beSStefan Roese 1159a47a12beSStefan Roese /* Though all the LBIU Local Access Windows and LBC Banks will be 1160a47a12beSStefan Roese * initialized in the C code, we'd better configure boot ROM's 1161a47a12beSStefan Roese * window 0 and bank 0 correctly at here. 1162a47a12beSStefan Roese */ 1163a47a12beSStefan Roeseremap_flash_by_law0: 1164a47a12beSStefan Roese /* Initialize the BR0 with the boot ROM starting address. */ 1165a47a12beSStefan Roese lwz r4, BR0(r3) 1166a47a12beSStefan Roese li r5, 0x7FFF 1167a47a12beSStefan Roese and r4, r4, r5 1168a47a12beSStefan Roese lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1169a47a12beSStefan Roese ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1170a47a12beSStefan Roese or r5, r5, r4 1171a47a12beSStefan Roese stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1172a47a12beSStefan Roese 1173a47a12beSStefan Roese lwz r4, OR0(r3) 1174a47a12beSStefan Roese lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1175a47a12beSStefan Roese or r4, r4, r5 1176a47a12beSStefan Roese stw r4, OR0(r3) 1177a47a12beSStefan Roese 1178a47a12beSStefan Roese lis r4, (CONFIG_SYS_FLASH_BASE)@h 1179a47a12beSStefan Roese ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1180a47a12beSStefan Roese stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1181a47a12beSStefan Roese 1182a47a12beSStefan Roese /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1183a47a12beSStefan Roese lis r4, (0x80000012)@h 1184a47a12beSStefan Roese ori r4, r4, (0x80000012)@l 1185a47a12beSStefan Roese li r5, CONFIG_SYS_FLASH_SIZE 1186a47a12beSStefan Roese1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1187a47a12beSStefan Roese addi r4, r4, 1 1188a47a12beSStefan Roese bne 1b 1189a47a12beSStefan Roese stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1190a47a12beSStefan Roese 1191a47a12beSStefan Roese 1192a47a12beSStefan Roese xor r4, r4, r4 1193a47a12beSStefan Roese stw r4, LBLAWBAR1(r3) 1194a47a12beSStefan Roese stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1195e45c98adSJoakim Tjernlund /* Wait for HW to catch up */ 1196e45c98adSJoakim Tjernlund lwz r4, LBLAWAR1(r3) 1197e45c98adSJoakim Tjernlund twi 0,r4,0 1198e45c98adSJoakim Tjernlund isync 1199a47a12beSStefan Roese blr 1200a47a12beSStefan Roese#endif /* CONFIG_SYS_FLASHBOOT */ 1201