1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * CPU specific code for the MPC83xx family. 25 * 26 * Derived from the MPC8260 and MPC85xx. 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <mpc83xx.h> 33 #include <asm/processor.h> 34 #include <libfdt.h> 35 #include <tsec.h> 36 #include <netdev.h> 37 #include <fsl_esdhc.h> 38 #ifdef CONFIG_BOOTCOUNT_LIMIT 39 #include <asm/immap_qe.h> 40 #include <asm/io.h> 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int checkcpu(void) 46 { 47 volatile immap_t *immr; 48 ulong clock = gd->cpu_clk; 49 u32 pvr = get_pvr(); 50 u32 spridr; 51 char buf[32]; 52 int i; 53 54 const struct cpu_type { 55 char name[15]; 56 u32 partid; 57 } cpu_type_list [] = { 58 CPU_TYPE_ENTRY(8308), 59 CPU_TYPE_ENTRY(8311), 60 CPU_TYPE_ENTRY(8313), 61 CPU_TYPE_ENTRY(8314), 62 CPU_TYPE_ENTRY(8315), 63 CPU_TYPE_ENTRY(8321), 64 CPU_TYPE_ENTRY(8323), 65 CPU_TYPE_ENTRY(8343), 66 CPU_TYPE_ENTRY(8347_TBGA_), 67 CPU_TYPE_ENTRY(8347_PBGA_), 68 CPU_TYPE_ENTRY(8349), 69 CPU_TYPE_ENTRY(8358_TBGA_), 70 CPU_TYPE_ENTRY(8358_PBGA_), 71 CPU_TYPE_ENTRY(8360), 72 CPU_TYPE_ENTRY(8377), 73 CPU_TYPE_ENTRY(8378), 74 CPU_TYPE_ENTRY(8379), 75 }; 76 77 immr = (immap_t *)CONFIG_SYS_IMMR; 78 79 puts("CPU: "); 80 81 switch (pvr & 0xffff0000) { 82 case PVR_E300C1: 83 printf("e300c1, "); 84 break; 85 86 case PVR_E300C2: 87 printf("e300c2, "); 88 break; 89 90 case PVR_E300C3: 91 printf("e300c3, "); 92 break; 93 94 case PVR_E300C4: 95 printf("e300c4, "); 96 break; 97 98 default: 99 printf("Unknown core, "); 100 } 101 102 spridr = immr->sysconf.spridr; 103 104 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 105 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { 106 puts("MPC"); 107 puts(cpu_type_list[i].name); 108 if (IS_E_PROCESSOR(spridr)) 109 puts("E"); 110 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY || 111 SPR_FAMILY(spridr) == SPR_836X_FAMILY) && 112 REVID_MAJOR(spridr) >= 2) 113 puts("A"); 114 printf(", Rev: %d.%d", REVID_MAJOR(spridr), 115 REVID_MINOR(spridr)); 116 break; 117 } 118 119 if (i == ARRAY_SIZE(cpu_type_list)) 120 printf("(SPRIDR %08x unknown), ", spridr); 121 122 printf(" at %s MHz, ", strmhz(buf, clock)); 123 124 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk)); 125 126 return 0; 127 } 128 129 130 /* 131 * Program a UPM with the code supplied in the table. 132 * 133 * The 'dummy' variable is used to increment the MAD. 'dummy' is 134 * supposed to be a pointer to the memory of the device being 135 * programmed by the UPM. The data in the MDR is written into 136 * memory and the MAD is incremented every time there's a write 137 * to 'dummy'. Unfortunately, the current prototype for this 138 * function doesn't allow for passing the address of this 139 * device, and changing the prototype will break a number lots 140 * of other code, so we need to use a round-about way of finding 141 * the value for 'dummy'. 142 * 143 * The value can be extracted from the base address bits of the 144 * Base Register (BR) associated with the specific UPM. To find 145 * that BR, we need to scan all 8 BRs until we find the one that 146 * has its MSEL bits matching the UPM we want. Once we know the 147 * right BR, we can extract the base address bits from it. 148 * 149 * The MxMR and the BR and OR of the chosen bank should all be 150 * configured before calling this function. 151 * 152 * Parameters: 153 * upm: 0=UPMA, 1=UPMB, 2=UPMC 154 * table: Pointer to an array of values to program 155 * size: Number of elements in the array. Must be 64 or less. 156 */ 157 void upmconfig (uint upm, uint *table, uint size) 158 { 159 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 160 volatile fsl_lbus_t *lbus = &immap->lbus; 161 volatile uchar *dummy = NULL; 162 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ 163 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */ 164 uint i; 165 166 /* Scan all the banks to determine the base address of the device */ 167 for (i = 0; i < 8; i++) { 168 if ((lbus->bank[i].br & BR_MSEL) == msel) { 169 dummy = (uchar *) (lbus->bank[i].br & BR_BA); 170 break; 171 } 172 } 173 174 if (!dummy) { 175 printf("Error: %s() could not find matching BR\n", __FUNCTION__); 176 hang(); 177 } 178 179 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */ 180 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000; 181 182 for (i = 0; i < size; i++) { 183 lbus->mdr = table[i]; 184 __asm__ __volatile__ ("sync"); 185 *dummy = 0; /* Write the value to memory and increment MAD */ 186 __asm__ __volatile__ ("sync"); 187 while(((*mxmr & 0x3f) != ((i + 1) & 0x3f))); 188 } 189 190 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ 191 *mxmr &= 0xCFFFFFC0; 192 } 193 194 195 int 196 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 197 { 198 ulong msr; 199 #ifndef MPC83xx_RESET 200 ulong addr; 201 #endif 202 203 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 204 205 puts("Resetting the board.\n"); 206 207 #ifdef MPC83xx_RESET 208 209 /* Interrupts and MMU off */ 210 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 211 212 msr &= ~( MSR_EE | MSR_IR | MSR_DR); 213 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 214 215 /* enable Reset Control Reg */ 216 immap->reset.rpr = 0x52535445; 217 __asm__ __volatile__ ("sync"); 218 __asm__ __volatile__ ("isync"); 219 220 /* confirm Reset Control Reg is enabled */ 221 while(!((immap->reset.rcer) & RCER_CRE)); 222 223 udelay(200); 224 225 /* perform reset, only one bit */ 226 immap->reset.rcr = RCR_SWHR; 227 228 #else /* ! MPC83xx_RESET */ 229 230 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ 231 232 /* Interrupts and MMU off */ 233 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 234 235 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); 236 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 237 238 /* 239 * Trying to execute the next instruction at a non-existing address 240 * should cause a machine check, resulting in reset 241 */ 242 addr = CONFIG_SYS_RESET_ADDRESS; 243 244 ((void (*)(void)) addr) (); 245 #endif /* MPC83xx_RESET */ 246 247 return 1; 248 } 249 250 251 /* 252 * Get timebase clock frequency (like cpu_clk in Hz) 253 */ 254 255 unsigned long get_tbclk(void) 256 { 257 ulong tbclk; 258 259 tbclk = (gd->bus_clk + 3L) / 4L; 260 261 return tbclk; 262 } 263 264 265 #if defined(CONFIG_WATCHDOG) 266 void watchdog_reset (void) 267 { 268 int re_enable = disable_interrupts(); 269 270 /* Reset the 83xx watchdog */ 271 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 272 immr->wdt.swsrr = 0x556c; 273 immr->wdt.swsrr = 0xaa39; 274 275 if (re_enable) 276 enable_interrupts (); 277 } 278 #endif 279 280 /* 281 * Initializes on-chip ethernet controllers. 282 * to override, implement board_eth_init() 283 */ 284 int cpu_eth_init(bd_t *bis) 285 { 286 #if defined(CONFIG_UEC_ETH) 287 uec_standard_init(bis); 288 #endif 289 290 #if defined(CONFIG_TSEC_ENET) 291 tsec_standard_init(bis); 292 #endif 293 return 0; 294 } 295 296 /* 297 * Initializes on-chip MMC controllers. 298 * to override, implement board_mmc_init() 299 */ 300 int cpu_mmc_init(bd_t *bis) 301 { 302 #ifdef CONFIG_FSL_ESDHC 303 return fsl_esdhc_mmc_init(bis); 304 #else 305 return 0; 306 #endif 307 } 308