1*57cfeb51SThomas Chou /* 2*57cfeb51SThomas Chou * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 3*57cfeb51SThomas Chou * Scott McNutt <smcnutt@psyent.com> 4*57cfeb51SThomas Chou * 5*57cfeb51SThomas Chou * SPDX-License-Identifier: GPL-2.0+ 6*57cfeb51SThomas Chou */ 7*57cfeb51SThomas Chou 8*57cfeb51SThomas Chou #ifndef __ASM_NIOS2_H__ 9*57cfeb51SThomas Chou #define __ASM_NIOS2_H__ 10*57cfeb51SThomas Chou 11*57cfeb51SThomas Chou /*------------------------------------------------------------------------ 12*57cfeb51SThomas Chou * Control registers -- use with wrctl() & rdctl() 13*57cfeb51SThomas Chou *----------------------------------------------------------------------*/ 14*57cfeb51SThomas Chou #define CTL_STATUS 0 /* Processor status reg */ 15*57cfeb51SThomas Chou #define CTL_ESTATUS 1 /* Exception status reg */ 16*57cfeb51SThomas Chou #define CTL_BSTATUS 2 /* Break status reg */ 17*57cfeb51SThomas Chou #define CTL_IENABLE 3 /* Interrut enable reg */ 18*57cfeb51SThomas Chou #define CTL_IPENDING 4 /* Interrut pending reg */ 19*57cfeb51SThomas Chou 20*57cfeb51SThomas Chou /*------------------------------------------------------------------------ 21*57cfeb51SThomas Chou * Access to control regs 22*57cfeb51SThomas Chou *----------------------------------------------------------------------*/ 23*57cfeb51SThomas Chou 24*57cfeb51SThomas Chou #define rdctl(reg) __builtin_rdctl(reg) 25*57cfeb51SThomas Chou #define wrctl(reg, val) __builtin_wrctl(reg, val) 26*57cfeb51SThomas Chou 27*57cfeb51SThomas Chou /*------------------------------------------------------------------------ 28*57cfeb51SThomas Chou * Control reg bit masks 29*57cfeb51SThomas Chou *----------------------------------------------------------------------*/ 30*57cfeb51SThomas Chou #define STATUS_IE (1<<0) /* Interrupt enable */ 31*57cfeb51SThomas Chou #define STATUS_U (1<<1) /* User-mode */ 32*57cfeb51SThomas Chou 33*57cfeb51SThomas Chou /*------------------------------------------------------------------------ 34*57cfeb51SThomas Chou * Bit-31 Cache bypass -- only valid for data access. When data cache 35*57cfeb51SThomas Chou * is not implemented, bit 31 is ignored for compatibility. 36*57cfeb51SThomas Chou *----------------------------------------------------------------------*/ 37*57cfeb51SThomas Chou #define CACHE_BYPASS(a) ((a) | 0x80000000) 38*57cfeb51SThomas Chou #define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) 39*57cfeb51SThomas Chou 40*57cfeb51SThomas Chou #endif /* __ASM_NIOS2_H__ */ 41