1*7e812f2eSThomas Chou #ifndef __ASM_NIOS2_DMA_MAPPING_H 2*7e812f2eSThomas Chou #define __ASM_NIOS2_DMA_MAPPING_H 3*7e812f2eSThomas Chou 4*7e812f2eSThomas Chou /* dma_alloc_coherent() return cache-line aligned allocation which is mapped 5*7e812f2eSThomas Chou * to uncached io region. 6*7e812f2eSThomas Chou * 7*7e812f2eSThomas Chou * IO_REGION_BASE should be defined in board config header file 8*7e812f2eSThomas Chou * 0x80000000 for nommu, 0xe0000000 for mmu 9*7e812f2eSThomas Chou */ 10*7e812f2eSThomas Chou 11*7e812f2eSThomas Chou static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) 12*7e812f2eSThomas Chou { 13*7e812f2eSThomas Chou void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE); 14*7e812f2eSThomas Chou if (!addr) 15*7e812f2eSThomas Chou return 0; 16*7e812f2eSThomas Chou flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE); 17*7e812f2eSThomas Chou *handle = ((unsigned long)addr + 18*7e812f2eSThomas Chou (CONFIG_SYS_DCACHELINE_SIZE - 1)) & 19*7e812f2eSThomas Chou ~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE); 20*7e812f2eSThomas Chou return (void *)(*handle | IO_REGION_BASE); 21*7e812f2eSThomas Chou } 22*7e812f2eSThomas Chou 23*7e812f2eSThomas Chou #endif /* __ASM_NIOS2_DMA_MAPPING_H */ 24