1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 3819833afSPeter Tyser * Scott McNutt <smcnutt@psyent.com> 4819833afSPeter Tyser * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6819833afSPeter Tyser */ 7819833afSPeter Tyser 8819833afSPeter Tyser #ifndef __ASM_NIOS2_CACHE_H_ 9819833afSPeter Tyser #define __ASM_NIOS2_CACHE_H_ 10819833afSPeter Tyser 11819833afSPeter Tyser extern void flush_dcache (unsigned long start, unsigned long size); 12819833afSPeter Tyser extern void flush_icache (unsigned long start, unsigned long size); 13819833afSPeter Tyser 146fa6035fSAnton Staaf /* 156fa6035fSAnton Staaf * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32 166fa6035fSAnton Staaf * bytes. If the board configuration has not specified one we default to the 176fa6035fSAnton Staaf * largest of these values for alignment of DMA buffers. 186fa6035fSAnton Staaf */ 196fa6035fSAnton Staaf #ifdef CONFIG_SYS_CACHELINE_SIZE 206fa6035fSAnton Staaf #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 216fa6035fSAnton Staaf #else 226fa6035fSAnton Staaf #define ARCH_DMA_MINALIGN 32 236fa6035fSAnton Staaf #endif 246fa6035fSAnton Staaf 25819833afSPeter Tyser #endif /* __ASM_NIOS2_CACHE_H_ */ 26