1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 3819833afSPeter Tyser * Scott McNutt <smcnutt@psyent.com> 4819833afSPeter Tyser * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6819833afSPeter Tyser */ 7819833afSPeter Tyser 8819833afSPeter Tyser #ifndef __ASM_NIOS2_CACHE_H_ 9819833afSPeter Tyser #define __ASM_NIOS2_CACHE_H_ 10819833afSPeter Tyser 116fa6035fSAnton Staaf /* 12*21ff7344SThomas Chou * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 13*21ff7344SThomas Chou * 16, and 32 bytes. We default to the largest of these values for 14*21ff7344SThomas Chou * alignment of DMA buffers. 156fa6035fSAnton Staaf */ 166fa6035fSAnton Staaf #define ARCH_DMA_MINALIGN 32 176fa6035fSAnton Staaf 18819833afSPeter Tyser #endif /* __ASM_NIOS2_CACHE_H_ */ 19