1/* 2 * Copyright (C) 2013 Altera Corporation 3 * 4 * This file is generated by sopc2dts. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9/dts-v1/; 10 11/ { 12 model = "altr,qsys_ghrd_3c120"; 13 compatible = "altr,qsys_ghrd_3c120"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu: cpu@0x0 { 22 device_type = "cpu"; 23 compatible = "altr,nios2-1.0"; 24 reg = <0x00000000>; 25 interrupt-controller; 26 #interrupt-cells = <1>; 27 clock-frequency = <125000000>; 28 dcache-line-size = <32>; 29 icache-line-size = <32>; 30 dcache-size = <32768>; 31 icache-size = <32768>; 32 altr,implementation = "fast"; 33 altr,pid-num-bits = <8>; 34 altr,tlb-num-ways = <16>; 35 altr,tlb-num-entries = <128>; 36 altr,tlb-ptr-sz = <7>; 37 altr,has-div = <1>; 38 altr,has-mul = <1>; 39 altr,reset-addr = <0xc2800000>; 40 altr,fast-tlb-miss-addr = <0xc7fff400>; 41 altr,exception-addr = <0xd0000020>; 42 altr,has-initda = <1>; 43 altr,has-mmu = <1>; 44 }; 45 }; 46 47 memory@0 { 48 device_type = "memory"; 49 reg = <0x10000000 0x08000000>, 50 <0x07fff400 0x00000400>; 51 }; 52 53 sopc@0 { 54 device_type = "soc"; 55 ranges; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 compatible = "altr,avalon", "simple-bus"; 59 bus-frequency = <125000000>; 60 61 pb_cpu_to_io: bridge@0x8000000 { 62 compatible = "simple-bus"; 63 reg = <0x08000000 0x00800000>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges = <0x00002000 0x08002000 0x00002000>, 67 <0x00004000 0x08004000 0x00000400>, 68 <0x00004400 0x08004400 0x00000040>, 69 <0x00004800 0x08004800 0x00000040>, 70 <0x00004c80 0x08004c80 0x00000020>, 71 <0x00004cc0 0x08004cc0 0x00000010>, 72 <0x00004ce0 0x08004ce0 0x00000010>, 73 <0x00004d00 0x08004d00 0x00000010>, 74 <0x00004d50 0x08004d50 0x00000008>, 75 <0x00008000 0x08008000 0x00000020>, 76 <0x00400000 0x08400000 0x00000020>; 77 78 timer_1ms: timer@0x400000 { 79 compatible = "altr,timer-1.0"; 80 reg = <0x00400000 0x00000020>; 81 interrupt-parent = <&cpu>; 82 interrupts = <11>; 83 clock-frequency = <125000000>; 84 }; 85 86 timer_0: timer@0x8000 { 87 compatible = "altr,timer-1.0"; 88 reg = < 0x00008000 0x00000020 >; 89 interrupt-parent = < &cpu >; 90 interrupts = < 5 >; 91 clock-frequency = < 125000000 >; 92 }; 93 94 jtag_uart: serial@0x4d50 { 95 compatible = "altr,juart-1.0"; 96 reg = <0x00004d50 0x00000008>; 97 interrupt-parent = <&cpu>; 98 interrupts = <1>; 99 }; 100 101 tse_mac: ethernet@0x4000 { 102 compatible = "altr,tse-1.0"; 103 reg = <0x00004000 0x00000400>, 104 <0x00004400 0x00000040>, 105 <0x00004800 0x00000040>, 106 <0x00002000 0x00002000>; 107 reg-names = "control_port", "rx_csr", "tx_csr", "s1"; 108 interrupt-parent = <&cpu>; 109 interrupts = <2 3>; 110 interrupt-names = "rx_irq", "tx_irq"; 111 rx-fifo-depth = <8192>; 112 tx-fifo-depth = <8192>; 113 max-frame-size = <1518>; 114 local-mac-address = [ 00 00 00 00 00 00 ]; 115 phy-mode = "rgmii-id"; 116 phy-handle = <&phy0>; 117 tse_mac_mdio: mdio { 118 compatible = "altr,tse-mdio"; 119 #address-cells = <1>; 120 #size-cells = <0>; 121 phy0: ethernet-phy@18 { 122 reg = <18>; 123 device_type = "ethernet-phy"; 124 }; 125 }; 126 }; 127 128 uart: serial@0x4c80 { 129 compatible = "altr,uart-1.0"; 130 reg = <0x00004c80 0x00000020>; 131 interrupt-parent = <&cpu>; 132 interrupts = <10>; 133 current-speed = <115200>; 134 clock-frequency = <62500000>; 135 }; 136 137 user_led_pio_8out: gpio@0x4cc0 { 138 compatible = "altr,pio-1.0"; 139 reg = <0x00004cc0 0x00000010>; 140 resetvalue = <255>; 141 altr,gpio-bank-width = <8>; 142 #gpio-cells = <2>; 143 gpio-controller; 144 gpio-bank-name = "led"; 145 }; 146 147 user_dipsw_pio_8in: gpio@0x4ce0 { 148 compatible = "altr,pio-1.0"; 149 reg = <0x00004ce0 0x00000010>; 150 interrupt-parent = <&cpu>; 151 interrupts = <8>; 152 edge_type = <2>; 153 level_trigger = <0>; 154 resetvalue = <0>; 155 altr,gpio-bank-width = <8>; 156 #gpio-cells = <2>; 157 gpio-controller; 158 gpio-bank-name = "dipsw"; 159 }; 160 161 user_pb_pio_4in: gpio@0x4d00 { 162 compatible = "altr,pio-1.0"; 163 reg = <0x00004d00 0x00000010>; 164 interrupt-parent = <&cpu>; 165 interrupts = <9>; 166 edge_type = <2>; 167 level_trigger = <0>; 168 resetvalue = <0>; 169 altr,gpio-bank-width = <4>; 170 #gpio-cells = <2>; 171 gpio-controller; 172 gpio-bank-name = "pb"; 173 }; 174 }; 175 176 cfi_flash_64m: flash@0x0 { 177 compatible = "cfi-flash"; 178 reg = <0x00000000 0x04000000>; 179 bank-width = <2>; 180 device-width = <1>; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 184 partition@800000 { 185 reg = <0x00800000 0x01e00000>; 186 label = "JFFS2 Filesystem"; 187 }; 188 }; 189 }; 190 191 chosen { 192 bootargs = "debug console=ttyJ0,115200"; 193 stdout-path = &jtag_uart; 194 }; 195}; 196