100f892fcSMacpaul Lin /* 200f892fcSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 300f892fcSMacpaul Lin * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 400f892fcSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 500f892fcSMacpaul Lin * 600f892fcSMacpaul Lin * See file CREDITS for list of people who contributed to this 700f892fcSMacpaul Lin * project. 800f892fcSMacpaul Lin * 900f892fcSMacpaul Lin * This program is free software; you can redistribute it and/or 1000f892fcSMacpaul Lin * modify it under the terms of the GNU General Public License as 1100f892fcSMacpaul Lin * published by the Free Software Foundation; either version 2 of 1200f892fcSMacpaul Lin * the License, or (at your option) any later version. 1300f892fcSMacpaul Lin * 1400f892fcSMacpaul Lin * This program is distributed in the hope that it will be useful, 1500f892fcSMacpaul Lin * but WITHOUT ANY WARRANTY; without even the implied warranty of 1600f892fcSMacpaul Lin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1700f892fcSMacpaul Lin * GNU General Public License for more details. 1800f892fcSMacpaul Lin * 1900f892fcSMacpaul Lin * You should have received a copy of the GNU General Public License 2000f892fcSMacpaul Lin * along with this program; if not, write to the Free Software 2100f892fcSMacpaul Lin * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2200f892fcSMacpaul Lin * MA 02111-1307 USA 2300f892fcSMacpaul Lin */ 2400f892fcSMacpaul Lin 2500f892fcSMacpaul Lin #ifndef _ASM_CACHE_H 2600f892fcSMacpaul Lin #define _ASM_CACHE_H 2700f892fcSMacpaul Lin 2800f892fcSMacpaul Lin /* cache */ 2900f892fcSMacpaul Lin int icache_status(void); 3000f892fcSMacpaul Lin void icache_enable(void); 3100f892fcSMacpaul Lin void icache_disable(void); 3200f892fcSMacpaul Lin int dcache_status(void); 3300f892fcSMacpaul Lin void dcache_enable(void); 3400f892fcSMacpaul Lin void dcache_disable(void); 3500f892fcSMacpaul Lin 3600f892fcSMacpaul Lin #define DEFINE_GET_SYS_REG(reg) \ 3700f892fcSMacpaul Lin static inline unsigned long GET_##reg(void) \ 3800f892fcSMacpaul Lin { \ 3900f892fcSMacpaul Lin unsigned long val; \ 4000f892fcSMacpaul Lin __asm__ volatile ( \ 4100f892fcSMacpaul Lin "mfsr %0, $"#reg : "=&r" (val) : : "memory" \ 4200f892fcSMacpaul Lin ); \ 4300f892fcSMacpaul Lin return val; \ 4400f892fcSMacpaul Lin } 4500f892fcSMacpaul Lin 4600f892fcSMacpaul Lin enum cache_t {ICACHE, DCACHE}; 4700f892fcSMacpaul Lin DEFINE_GET_SYS_REG(ICM_CFG); 4800f892fcSMacpaul Lin DEFINE_GET_SYS_REG(DCM_CFG); 4900f892fcSMacpaul Lin #define ICM_CFG_OFF_ISZ 6 /* I-cache line size */ 5000f892fcSMacpaul Lin #define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) 5100f892fcSMacpaul Lin #define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ 5200f892fcSMacpaul Lin #define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) 5300f892fcSMacpaul Lin 54*466e73b1SMacpaul Lin /* 55*466e73b1SMacpaul Lin * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. 56*466e73b1SMacpaul Lin * We use that value for aligning DMA buffers unless the board config has 57*466e73b1SMacpaul Lin * specified an alternate cache line size. 58*466e73b1SMacpaul Lin */ 59*466e73b1SMacpaul Lin #ifdef CONFIG_SYS_CACHELINE_SIZE 60*466e73b1SMacpaul Lin #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 61*466e73b1SMacpaul Lin #else 62*466e73b1SMacpaul Lin #define ARCH_DMA_MINALIGN 32 63*466e73b1SMacpaul Lin #endif 64*466e73b1SMacpaul Lin 6500f892fcSMacpaul Lin #endif /* _ASM_CACHE_H */ 66