100f892fcSMacpaul Lin /* 200f892fcSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 300f892fcSMacpaul Lin * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 400f892fcSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 500f892fcSMacpaul Lin * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 700f892fcSMacpaul Lin */ 800f892fcSMacpaul Lin 900f892fcSMacpaul Lin #ifndef _ASM_CACHE_H 1000f892fcSMacpaul Lin #define _ASM_CACHE_H 1100f892fcSMacpaul Lin 1200f892fcSMacpaul Lin /* cache */ 1300f892fcSMacpaul Lin int icache_status(void); 1400f892fcSMacpaul Lin void icache_enable(void); 1500f892fcSMacpaul Lin void icache_disable(void); 1600f892fcSMacpaul Lin int dcache_status(void); 1700f892fcSMacpaul Lin void dcache_enable(void); 1800f892fcSMacpaul Lin void dcache_disable(void); 1900f892fcSMacpaul Lin 2000f892fcSMacpaul Lin #define DEFINE_GET_SYS_REG(reg) \ 2100f892fcSMacpaul Lin static inline unsigned long GET_##reg(void) \ 2200f892fcSMacpaul Lin { \ 2300f892fcSMacpaul Lin unsigned long val; \ 2400f892fcSMacpaul Lin __asm__ volatile ( \ 2500f892fcSMacpaul Lin "mfsr %0, $"#reg : "=&r" (val) : : "memory" \ 2600f892fcSMacpaul Lin ); \ 2700f892fcSMacpaul Lin return val; \ 2800f892fcSMacpaul Lin } 2900f892fcSMacpaul Lin 3000f892fcSMacpaul Lin enum cache_t {ICACHE, DCACHE}; 3100f892fcSMacpaul Lin DEFINE_GET_SYS_REG(ICM_CFG); 3200f892fcSMacpaul Lin DEFINE_GET_SYS_REG(DCM_CFG); 3300f892fcSMacpaul Lin #define ICM_CFG_OFF_ISZ 6 /* I-cache line size */ 3400f892fcSMacpaul Lin #define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) 3500f892fcSMacpaul Lin #define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ 3600f892fcSMacpaul Lin #define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) 3700f892fcSMacpaul Lin 38466e73b1SMacpaul Lin /* 39466e73b1SMacpaul Lin * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. 40466e73b1SMacpaul Lin * We use that value for aligning DMA buffers unless the board config has 41466e73b1SMacpaul Lin * specified an alternate cache line size. 42466e73b1SMacpaul Lin */ 43466e73b1SMacpaul Lin #ifdef CONFIG_SYS_CACHELINE_SIZE 44466e73b1SMacpaul Lin #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 45466e73b1SMacpaul Lin #else 46466e73b1SMacpaul Lin #define ARCH_DMA_MINALIGN 32 47466e73b1SMacpaul Lin #endif 48466e73b1SMacpaul Lin 4900f892fcSMacpaul Lin #endif /* _ASM_CACHE_H */ 50