1445a886dSMacpaul Lin /* 2445a886dSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 3445a886dSMacpaul Lin * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4445a886dSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5445a886dSMacpaul Lin * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7445a886dSMacpaul Lin */ 8445a886dSMacpaul Lin 9445a886dSMacpaul Lin #ifndef __AG101_H 10445a886dSMacpaul Lin #define __AG101_H 11445a886dSMacpaul Lin 12445a886dSMacpaul Lin /* Hardware register bases */ 13445a886dSMacpaul Lin 14445a886dSMacpaul Lin /* AHB Controller */ 15445a886dSMacpaul Lin #define CONFIG_FTAHBC020S_BASE 0x90100000 16445a886dSMacpaul Lin /* Static Memory Controller (SRAM) */ 17445a886dSMacpaul Lin #define CONFIG_FTSMC020_BASE 0x90200000 18445a886dSMacpaul Lin /* FTSDMC021 SDRAM Controller */ 19445a886dSMacpaul Lin #define CONFIG_FTSDMC021_BASE 0x90300000 20445a886dSMacpaul Lin /* DMA Controller */ 21445a886dSMacpaul Lin #define CONFIG_FTDMAC020_BASE 0x90400000 22445a886dSMacpaul Lin /* AHB-to-APB Bridge */ 23445a886dSMacpaul Lin #define CONFIG_FTAPBBRG020S_01_BASE 0x90500000 24445a886dSMacpaul Lin /* LCD Controller */ 25445a886dSMacpaul Lin #define CONFIG_FTLCDC100_BASE 0x90600000 26445a886dSMacpaul Lin /* Reserved */ 27445a886dSMacpaul Lin #define CONFIG_RESERVED_01_BASE 0x90700000 28445a886dSMacpaul Lin /* Reserved */ 29445a886dSMacpaul Lin #define CONFIG_RESERVED_02_BASE 0x90800000 30445a886dSMacpaul Lin /* Ethernet */ 31445a886dSMacpaul Lin #define CONFIG_FTMAC100_BASE 0x90900000 32445a886dSMacpaul Lin /* External USB host */ 33445a886dSMacpaul Lin #define CONFIG_EXT_USB_HOST_BASE 0x90A00000 34445a886dSMacpaul Lin /* USB Device */ 35445a886dSMacpaul Lin #define CONFIG_USB_DEV_BASE 0x90B00000 36445a886dSMacpaul Lin /* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */ 37445a886dSMacpaul Lin #define CONFIG_EXT_AHBPCIBRG_BASE 0x90C00000 38445a886dSMacpaul Lin /* Reserved */ 39445a886dSMacpaul Lin #define CONFIG_RESERVED_03_BASE 0x90D00000 40445a886dSMacpaul Lin /* External AHB-to-APB Bridger (FTAPBBRG020S_02) */ 41445a886dSMacpaul Lin #define CONFIG_EXT_AHBAPBBRG_BASE 0x90E00000 42445a886dSMacpaul Lin /* External AHB slave1 (LCD) */ 43445a886dSMacpaul Lin #define CONFIG_EXT_AHBSLAVE01_BASE 0x90F00000 44445a886dSMacpaul Lin /* External AHB slave2 (FUSBH200) */ 45445a886dSMacpaul Lin #define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000 46445a886dSMacpaul Lin 47445a886dSMacpaul Lin /* DEBUG LED */ 48445a886dSMacpaul Lin #define CONFIG_DEBUG_LED 0x902FFFFC 49445a886dSMacpaul Lin 50445a886dSMacpaul Lin /* APB Device definitions */ 51445a886dSMacpaul Lin 52445a886dSMacpaul Lin /* Power Management Unit */ 53445a886dSMacpaul Lin #define CONFIG_FTPMU010_BASE 0x98100000 54445a886dSMacpaul Lin /* BT UART 2/IrDA (UART 01 in Linux) */ 55445a886dSMacpaul Lin #define CONFIG_FTUART010_01_BASE 0x98300000 56445a886dSMacpaul Lin /* Counter/Timers */ 57445a886dSMacpaul Lin #define CONFIG_FTTMR010_BASE 0x98400000 58445a886dSMacpaul Lin /* Watchdog Timer */ 59445a886dSMacpaul Lin #define CONFIG_FTWDT010_BASE 0x98500000 60445a886dSMacpaul Lin /* Real Time Clock */ 61445a886dSMacpaul Lin #define CONFIG_FTRTC010_BASE 0x98600000 62445a886dSMacpaul Lin /* GPIO */ 63445a886dSMacpaul Lin #define CONFIG_FTGPIO010_BASE 0x98700000 64445a886dSMacpaul Lin /* Interrupt Controller */ 65445a886dSMacpaul Lin #define CONFIG_FTINTC010_BASE 0x98800000 66445a886dSMacpaul Lin /* I2C */ 67445a886dSMacpaul Lin #define CONFIG_FTIIC010_BASE 0x98A00000 68445a886dSMacpaul Lin /* Reserved */ 69445a886dSMacpaul Lin #define CONFIG_RESERVED_04_BASE 0x98C00000 70445a886dSMacpaul Lin /* Compat Flash Controller */ 71445a886dSMacpaul Lin #define CONFIG_FTCFC010_BASE 0x98D00000 72445a886dSMacpaul Lin /* SD Controller */ 73445a886dSMacpaul Lin #define CONFIG_FTSDC010_BASE 0x98E00000 74445a886dSMacpaul Lin 75445a886dSMacpaul Lin /* Synchronous Serial Port Controller (SSP) I2S/AC97 */ 76445a886dSMacpaul Lin #define CONFIG_FTSSP010_02_BASE 0x99400000 77445a886dSMacpaul Lin /* ST UART ? SSP 02 (UART 02 in Linux) */ 78445a886dSMacpaul Lin #define CONFIG_FTUART010_02_BASE 0x99600000 79445a886dSMacpaul Lin 80445a886dSMacpaul Lin /* The following address was not defined in Linux */ 81445a886dSMacpaul Lin 82445a886dSMacpaul Lin /* FF UART 3 */ 83445a886dSMacpaul Lin #define CONFIG_FTUART010_03_BASE 0x98200000 84445a886dSMacpaul Lin /* Synchronous Serial Port Controller (SSP) 01 */ 85445a886dSMacpaul Lin #define CONFIG_FTSSP010_01_BASE 0x98B00000 86445a886dSMacpaul Lin /* IrDA */ 87445a886dSMacpaul Lin #define CONFIG_IRDA_BASE 0x98900000 88445a886dSMacpaul Lin /* PWM - Pulse Width Modulator Controller */ 89445a886dSMacpaul Lin #define CONFIG_PMW_BASE 0x99100000 90445a886dSMacpaul Lin 91445a886dSMacpaul Lin #endif /* __AG101_H */ 92