1*b841b6e9Srick /* 2*b841b6e9Srick * Copyright (C) 2016 Andes Technology Corporation 3*b841b6e9Srick * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4*b841b6e9Srick * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5*b841b6e9Srick * 6*b841b6e9Srick * SPDX-License-Identifier: GPL-2.0+ 7*b841b6e9Srick */ 8*b841b6e9Srick 9*b841b6e9Srick #ifndef __AE3XX_H 10*b841b6e9Srick #define __AE3XX_H 11*b841b6e9Srick 12*b841b6e9Srick /* Hardware register bases */ 13*b841b6e9Srick 14*b841b6e9Srick /* Static Memory Controller (SRAM) */ 15*b841b6e9Srick #define CONFIG_FTSMC020_BASE 0xe0400000 16*b841b6e9Srick /* DMA Controller */ 17*b841b6e9Srick #define CONFIG_FTDMAC020_BASE 0xf0c00000 18*b841b6e9Srick /* AHB-to-APB Bridge */ 19*b841b6e9Srick #define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000 20*b841b6e9Srick /* Reserved */ 21*b841b6e9Srick #define CONFIG_RESERVED_01_BASE 0xe0500000 22*b841b6e9Srick /* Reserved */ 23*b841b6e9Srick #define CONFIG_RESERVED_02_BASE 0xf0800000 24*b841b6e9Srick /* Reserved */ 25*b841b6e9Srick #define CONFIG_RESERVED_03_BASE 0xf0900000 26*b841b6e9Srick /* Ethernet */ 27*b841b6e9Srick #define CONFIG_FTMAC100_BASE 0xe0100000 28*b841b6e9Srick /* Reserved */ 29*b841b6e9Srick #define CONFIG_RESERVED_04_BASE 0xf1000000 30*b841b6e9Srick 31*b841b6e9Srick /* APB Device definitions */ 32*b841b6e9Srick 33*b841b6e9Srick /* UART1 */ 34*b841b6e9Srick #define CONFIG_FTUART010_01_BASE 0xf0200000 35*b841b6e9Srick /* UART2 */ 36*b841b6e9Srick #define CONFIG_FTUART010_02_BASE 0xf0300000 37*b841b6e9Srick /* Counter/Timers */ 38*b841b6e9Srick #define CONFIG_FTTMR010_BASE 0xf0400000 39*b841b6e9Srick /* Watchdog Timer */ 40*b841b6e9Srick #define CONFIG_FTWDT010_BASE 0xf0500000 41*b841b6e9Srick /* Real Time Clock */ 42*b841b6e9Srick #define CONFIG_FTRTC010_BASE 0xf0600000 43*b841b6e9Srick /* GPIO */ 44*b841b6e9Srick #define CONFIG_FTGPIO010_BASE 0xf0700000 45*b841b6e9Srick /* I2C */ 46*b841b6e9Srick #define CONFIG_FTIIC010_BASE 0xf0a00000 47*b841b6e9Srick /* SD Controller */ 48*b841b6e9Srick #define CONFIG_FTSDC010_BASE 0xf0e00000 49*b841b6e9Srick 50*b841b6e9Srick /* The following address was not defined in Linux */ 51*b841b6e9Srick 52*b841b6e9Srick /* Synchronous Serial Port Controller (SSP) 01 */ 53*b841b6e9Srick #define CONFIG_FTSSP010_01_BASE 0xf0d00000 54*b841b6e9Srick #endif /* __AE3XX_H */ 55