1/dts-v1/; 2/ { 3 compatible = "nds32 ae3xx"; 4 #address-cells = <1>; 5 #size-cells = <1>; 6 interrupt-parent = <&intc>; 7 8 aliases { 9 uart0 = &serial0; 10 } ; 11 12 chosen { 13 /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */ 14 bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; 15 stdout-path = "uart0:38400n8"; 16 tick-timer = &timer0; 17 }; 18 19 memory@0 { 20 device_type = "memory"; 21 reg = <0x00000000 0x40000000>; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 cpu@0 { 28 compatible = "andestech,n13"; 29 reg = <0>; 30 /* FIXME: to fill correct frqeuency */ 31 clock-frequency = <60000000>; 32 }; 33 }; 34 35 intc: interrupt-controller { 36 compatible = "andestech,atnointc010"; 37 #interrupt-cells = <1>; 38 interrupt-controller; 39 }; 40 41 serial0: serial@f0300000 { 42 compatible = "andestech,uart16550", "ns16550a"; 43 reg = <0xf0300000 0x1000>; 44 interrupts = <7 4>; 45 clock-frequency = <14745600>; 46 reg-shift = <2>; 47 reg-offset = <32>; 48 no-loopback-test = <1>; 49 }; 50 51 timer0: timer@f0400000 { 52 compatible = "andestech,atcpit100"; 53 reg = <0xf0400000 0x1000>; 54 interrupts = <2 4>; 55 clock-frequency = <30000000>; 56 }; 57 58 nor@0,0 { 59 compatible = "cfi-flash"; 60 reg = <0x88000000 0x1000>; 61 bank-width = <2>; 62 device-width = <1>; 63 }; 64 65}; 66