1*b841b6e9Srick/* 2*b841b6e9Srick * Copyright (C) 2011 Andes Technology Corporation 3*b841b6e9Srick * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4*b841b6e9Srick * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5*b841b6e9Srick * 6*b841b6e9Srick * SPDX-License-Identifier: GPL-2.0+ 7*b841b6e9Srick */ 8*b841b6e9Srick 9*b841b6e9Srick.pic 10*b841b6e9Srick 11*b841b6e9Srick.text 12*b841b6e9Srick 13*b841b6e9Srick#include <common.h> 14*b841b6e9Srick#include <config.h> 15*b841b6e9Srick 16*b841b6e9Srick#include <asm/macro.h> 17*b841b6e9Srick#include <generated/asm-offsets.h> 18*b841b6e9Srick 19*b841b6e9Srick/* 20*b841b6e9Srick * parameters for the SDRAM controller 21*b841b6e9Srick */ 22*b841b6e9Srick#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1) 23*b841b6e9Srick#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2) 24*b841b6e9Srick#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1) 25*b841b6e9Srick#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2) 26*b841b6e9Srick#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR) 27*b841b6e9Srick#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR) 28*b841b6e9Srick 29*b841b6e9Srick#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1 30*b841b6e9Srick#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2 31*b841b6e9Srick#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1 32*b841b6e9Srick#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2 33*b841b6e9Srick 34*b841b6e9Srick#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR 35*b841b6e9Srick#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR 36*b841b6e9Srick 37*b841b6e9Srick 38*b841b6e9Srick/* 39*b841b6e9Srick * for Orca and Emerald 40*b841b6e9Srick */ 41*b841b6e9Srick#define BOARD_ID_REG 0x104 42*b841b6e9Srick#define BOARD_ID_FAMILY_MASK 0xfff000 43*b841b6e9Srick#define BOARD_ID_FAMILY_V5 0x556000 44*b841b6e9Srick#define BOARD_ID_FAMILY_K7 0x74b000 45*b841b6e9Srick 46*b841b6e9Srick/* 47*b841b6e9Srick * parameters for the static memory controller 48*b841b6e9Srick */ 49*b841b6e9Srick#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR) 50*b841b6e9Srick#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR) 51*b841b6e9Srick 52*b841b6e9Srick#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG 53*b841b6e9Srick#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING 54*b841b6e9Srick 55*b841b6e9Srick/* 56*b841b6e9Srick * for Orca and Emerald 57*b841b6e9Srick */ 58*b841b6e9Srick#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4) 59*b841b6e9Srick#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 60*b841b6e9Srick 61*b841b6e9Srick/* 62*b841b6e9Srick * parameters for the pmu controoler 63*b841b6e9Srick */ 64*b841b6e9Srick#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0) 65*b841b6e9Srick 66*b841b6e9Srick/* 67*b841b6e9Srick * numeric 7 segment display 68*b841b6e9Srick */ 69*b841b6e9Srick.macro led, num 70*b841b6e9Srick write32 CONFIG_DEBUG_LED, \num 71*b841b6e9Srick.endm 72*b841b6e9Srick 73*b841b6e9Srick/* 74*b841b6e9Srick * Waiting for SDRAM to set up 75*b841b6e9Srick */ 76*b841b6e9Srick.macro wait_sdram 77*b841b6e9Srick li $r0, CONFIG_FTSDMC021_BASE 78*b841b6e9Srick1: 79*b841b6e9Srick lwi $r1, [$r0+FTSDMC021_CR2] 80*b841b6e9Srick bnez $r1, 1b 81*b841b6e9Srick.endm 82*b841b6e9Srick 83*b841b6e9Srick.globl mem_init 84*b841b6e9Srickmem_init: 85*b841b6e9Srick move $r11, $lp 86*b841b6e9Srick li $r0, SMC_BANK0_CR_A 87*b841b6e9Srick lwi $r1, [$r0+#0x00] 88*b841b6e9Srick ori $r1, $r1, 0x8f0 89*b841b6e9Srick xori $r1, $r1, 0x8f0 90*b841b6e9Srick /* 16-bit mode */ 91*b841b6e9Srick ori $r1, $r1, 0x60 92*b841b6e9Srick li $r2, 0x00153153 93*b841b6e9Srick swi $r1, [$r0+#0x00] 94*b841b6e9Srick swi $r2, [$r0+#0x04] 95*b841b6e9Srick move $lp, $r11 96*b841b6e9Srick ret 97*b841b6e9Srick 98*b841b6e9Srick#ifndef CONFIG_SKIP_LOWLEVEL_INIT 99*b841b6e9Srick.globl lowlevel_init 100*b841b6e9Sricklowlevel_init: 101*b841b6e9Srick move $r10, $lp 102*b841b6e9Srick jal remap 103*b841b6e9Srick 104*b841b6e9Srick#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) 105*b841b6e9Srick jal enable_fpu 106*b841b6e9Srick#endif 107*b841b6e9Srick ret $r10 108*b841b6e9Srick 109*b841b6e9Srickremap: 110*b841b6e9Srick move $r11, $lp 111*b841b6e9Srickrelo_base: 112*b841b6e9Srick mfusr $r0, $pc 113*b841b6e9Srick 114*b841b6e9Srick#ifdef CONFIG_MEM_REMAP 115*b841b6e9Srick li $r4, 0x00000000 116*b841b6e9Srick li $r5, 0x80000000 117*b841b6e9Srick la $r6, _end@GOTOFF 118*b841b6e9Srick1: 119*b841b6e9Srick lmw.bim $r12, [$r5], $r19 120*b841b6e9Srick smw.bim $r12, [$r4], $r19 121*b841b6e9Srick blt $r5, $r6, 1b 122*b841b6e9Srick#endif /* #ifdef CONFIG_MEM_REMAP */ 123*b841b6e9Srick move $lp, $r11 124*b841b6e9Srick2: 125*b841b6e9Srick ret 126*b841b6e9Srick 127*b841b6e9Srick /* 128*b841b6e9Srick * enable_fpu: 129*b841b6e9Srick * Some of Andes CPU version support FPU coprocessor, if so, 130*b841b6e9Srick * and toolchain support FPU instruction set, we should enable it. 131*b841b6e9Srick */ 132*b841b6e9Srick#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) 133*b841b6e9Srickenable_fpu: 134*b841b6e9Srick mfsr $r0, $CPU_VER /* enable FPU if it exists */ 135*b841b6e9Srick srli $r0, $r0, 3 136*b841b6e9Srick andi $r0, $r0, 1 137*b841b6e9Srick beqz $r0, 1f /* skip if no COP */ 138*b841b6e9Srick mfsr $r0, $FUCOP_EXIST 139*b841b6e9Srick srli $r0, $r0, 31 140*b841b6e9Srick beqz $r0, 1f /* skip if no FPU */ 141*b841b6e9Srick mfsr $r0, $FUCOP_CTL 142*b841b6e9Srick ori $r0, $r0, 1 143*b841b6e9Srick mtsr $r0, $FUCOP_CTL 144*b841b6e9Srick1: 145*b841b6e9Srick ret 146*b841b6e9Srick#endif 147*b841b6e9Srick 148*b841b6e9Srick#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ 149