1*1d3d0f1fSWills Wang /* 2*1d3d0f1fSWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3*1d3d0f1fSWills Wang * 4*1d3d0f1fSWills Wang * SPDX-License-Identifier: GPL-2.0+ 5*1d3d0f1fSWills Wang */ 6*1d3d0f1fSWills Wang 7*1d3d0f1fSWills Wang #include <common.h> 8*1d3d0f1fSWills Wang #include <asm/io.h> 9*1d3d0f1fSWills Wang #include <asm/addrspace.h> 10*1d3d0f1fSWills Wang #include <asm/types.h> 11*1d3d0f1fSWills Wang #include <mach/ath79.h> 12*1d3d0f1fSWills Wang #include <mach/ar71xx_regs.h> 13*1d3d0f1fSWills Wang 14*1d3d0f1fSWills Wang void _machine_restart(void) 15*1d3d0f1fSWills Wang { 16*1d3d0f1fSWills Wang void __iomem *base; 17*1d3d0f1fSWills Wang u32 reg = 0; 18*1d3d0f1fSWills Wang 19*1d3d0f1fSWills Wang base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, 20*1d3d0f1fSWills Wang MAP_NOCACHE); 21*1d3d0f1fSWills Wang if (soc_is_ar71xx()) 22*1d3d0f1fSWills Wang reg = AR71XX_RESET_REG_RESET_MODULE; 23*1d3d0f1fSWills Wang else if (soc_is_ar724x()) 24*1d3d0f1fSWills Wang reg = AR724X_RESET_REG_RESET_MODULE; 25*1d3d0f1fSWills Wang else if (soc_is_ar913x()) 26*1d3d0f1fSWills Wang reg = AR913X_RESET_REG_RESET_MODULE; 27*1d3d0f1fSWills Wang else if (soc_is_ar933x()) 28*1d3d0f1fSWills Wang reg = AR933X_RESET_REG_RESET_MODULE; 29*1d3d0f1fSWills Wang else if (soc_is_ar934x()) 30*1d3d0f1fSWills Wang reg = AR934X_RESET_REG_RESET_MODULE; 31*1d3d0f1fSWills Wang else if (soc_is_qca953x()) 32*1d3d0f1fSWills Wang reg = QCA953X_RESET_REG_RESET_MODULE; 33*1d3d0f1fSWills Wang else if (soc_is_qca955x()) 34*1d3d0f1fSWills Wang reg = QCA955X_RESET_REG_RESET_MODULE; 35*1d3d0f1fSWills Wang else if (soc_is_qca956x()) 36*1d3d0f1fSWills Wang reg = QCA956X_RESET_REG_RESET_MODULE; 37*1d3d0f1fSWills Wang else 38*1d3d0f1fSWills Wang puts("Reset register not defined for this SOC\n"); 39*1d3d0f1fSWills Wang 40*1d3d0f1fSWills Wang if (reg) 41*1d3d0f1fSWills Wang setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP); 42*1d3d0f1fSWills Wang 43*1d3d0f1fSWills Wang while (1) 44*1d3d0f1fSWills Wang /* NOP */; 45*1d3d0f1fSWills Wang } 46*1d3d0f1fSWills Wang 47*1d3d0f1fSWills Wang u32 get_bootstrap(void) 48*1d3d0f1fSWills Wang { 49*1d3d0f1fSWills Wang const void __iomem *base; 50*1d3d0f1fSWills Wang u32 reg = 0; 51*1d3d0f1fSWills Wang 52*1d3d0f1fSWills Wang base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, 53*1d3d0f1fSWills Wang MAP_NOCACHE); 54*1d3d0f1fSWills Wang if (soc_is_ar933x()) 55*1d3d0f1fSWills Wang reg = AR933X_RESET_REG_BOOTSTRAP; 56*1d3d0f1fSWills Wang else if (soc_is_ar934x()) 57*1d3d0f1fSWills Wang reg = AR934X_RESET_REG_BOOTSTRAP; 58*1d3d0f1fSWills Wang else if (soc_is_qca953x()) 59*1d3d0f1fSWills Wang reg = QCA953X_RESET_REG_BOOTSTRAP; 60*1d3d0f1fSWills Wang else if (soc_is_qca955x()) 61*1d3d0f1fSWills Wang reg = QCA955X_RESET_REG_BOOTSTRAP; 62*1d3d0f1fSWills Wang else if (soc_is_qca956x()) 63*1d3d0f1fSWills Wang reg = QCA956X_RESET_REG_BOOTSTRAP; 64*1d3d0f1fSWills Wang else 65*1d3d0f1fSWills Wang puts("Bootstrap register not defined for this SOC\n"); 66*1d3d0f1fSWills Wang 67*1d3d0f1fSWills Wang if (reg) 68*1d3d0f1fSWills Wang return readl(base + reg); 69*1d3d0f1fSWills Wang 70*1d3d0f1fSWills Wang return 0; 71*1d3d0f1fSWills Wang } 72