1 /* 2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 */ 8 9 #ifndef _MIPS_ASM_MALTA_H 10 #define _MIPS_ASM_MALTA_H 11 12 #define MALTA_GT_BASE 0x1be00000 13 #define MALTA_GT_PCIIO_BASE 0x18000000 14 #define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8) 15 16 #define MALTA_MSC01_BIU_BASE 0x1bc80000 17 #define MALTA_MSC01_PCI_BASE 0x1bd00000 18 #define MALTA_MSC01_PBC_BASE 0x1bd40000 19 #define MALTA_MSC01_IP1_BASE 0x1bc00000 20 #define MALTA_MSC01_IP1_SIZE 0x00400000 21 #define MALTA_MSC01_IP2_BASE1 0x10000000 22 #define MALTA_MSC01_IP2_SIZE1 0x08000000 23 #define MALTA_MSC01_IP2_BASE2 0x18000000 24 #define MALTA_MSC01_IP2_SIZE2 0x04000000 25 #define MALTA_MSC01_IP3_BASE 0x1c000000 26 #define MALTA_MSC01_IP3_SIZE 0x04000000 27 #define MALTA_MSC01_PCIMEM_BASE 0x10000000 28 #define MALTA_MSC01_PCIMEM_SIZE 0x10000000 29 #define MALTA_MSC01_PCIMEM_MAP 0x10000000 30 #define MALTA_MSC01_PCIIO_BASE 0x1b000000 31 #define MALTA_MSC01_PCIIO_SIZE 0x00800000 32 #define MALTA_MSC01_PCIIO_MAP 0x00000000 33 #define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8) 34 35 #define MALTA_ASCIIWORD 0x1f000410 36 #define MALTA_ASCIIPOS0 0x1f000418 37 #define MALTA_ASCIIPOS1 0x1f000420 38 #define MALTA_ASCIIPOS2 0x1f000428 39 #define MALTA_ASCIIPOS3 0x1f000430 40 #define MALTA_ASCIIPOS4 0x1f000438 41 #define MALTA_ASCIIPOS5 0x1f000440 42 #define MALTA_ASCIIPOS6 0x1f000448 43 #define MALTA_ASCIIPOS7 0x1f000450 44 45 #define MALTA_RESET_BASE 0x1f000500 46 #define GORESET 0x42 47 48 #define MALTA_FLASH_BASE 0x1fc00000 49 50 #define MALTA_REVISION 0x1fc00010 51 #define MALTA_REVISION_CORID_SHF 10 52 #define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF) 53 #define MALTA_REVISION_CORID_CORE_LV 1 54 #define MALTA_REVISION_CORID_CORE_FPGA6 14 55 56 #define PCI_CFG_PIIX4_PIRQRCA 0x60 57 #define PCI_CFG_PIIX4_PIRQRCB 0x61 58 #define PCI_CFG_PIIX4_PIRQRCC 0x62 59 #define PCI_CFG_PIIX4_PIRQRCD 0x63 60 61 #endif /* _MIPS_ASM_MALTA_H */ 62