xref: /rk3399_rockchip-uboot/arch/mips/include/asm/malta.h (revision e0ada6319bb3eb8bc1f97c00f05508ac0cfffc34)
15a4dcfacSGabor Juhos /*
25a4dcfacSGabor Juhos  * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
35a4dcfacSGabor Juhos  *
45a4dcfacSGabor Juhos  * This program is free software; you can redistribute it and/or modify it
55a4dcfacSGabor Juhos  * under the terms of the GNU General Public License version 2 as published
65a4dcfacSGabor Juhos  * by the Free Software Foundation.
75a4dcfacSGabor Juhos  */
85a4dcfacSGabor Juhos 
95a4dcfacSGabor Juhos #ifndef _MIPS_ASM_MALTA_H
105a4dcfacSGabor Juhos #define _MIPS_ASM_MALTA_H
115a4dcfacSGabor Juhos 
12ac12984dSGabor Juhos #define MALTA_GT_BASE			0x1be00000
13baf37f06SPaul Burton #define MALTA_GT_PCIIO_BASE		0x18000000
14baf37f06SPaul Burton #define MALTA_GT_UART0_BASE		(MALTA_GT_PCIIO_BASE + 0x3f8)
15baf37f06SPaul Burton 
16baf37f06SPaul Burton #define MALTA_MSC01_BIU_BASE		0x1bc80000
17baf37f06SPaul Burton #define MALTA_MSC01_PCI_BASE		0x1bd00000
18baf37f06SPaul Burton #define MALTA_MSC01_PBC_BASE		0x1bd40000
19baf37f06SPaul Burton #define MALTA_MSC01_IP1_BASE		0x1bc00000
20baf37f06SPaul Burton #define MALTA_MSC01_IP1_SIZE		0x00400000
21baf37f06SPaul Burton #define MALTA_MSC01_IP2_BASE1		0x10000000
22baf37f06SPaul Burton #define MALTA_MSC01_IP2_SIZE1		0x08000000
23baf37f06SPaul Burton #define MALTA_MSC01_IP2_BASE2		0x18000000
24baf37f06SPaul Burton #define MALTA_MSC01_IP2_SIZE2		0x04000000
25baf37f06SPaul Burton #define MALTA_MSC01_IP3_BASE		0x1c000000
26baf37f06SPaul Burton #define MALTA_MSC01_IP3_SIZE		0x04000000
27baf37f06SPaul Burton #define MALTA_MSC01_PCIMEM_BASE		0x10000000
28baf37f06SPaul Burton #define MALTA_MSC01_PCIMEM_SIZE		0x10000000
29baf37f06SPaul Burton #define MALTA_MSC01_PCIMEM_MAP		0x10000000
30baf37f06SPaul Burton #define MALTA_MSC01_PCIIO_BASE		0x1b000000
31baf37f06SPaul Burton #define MALTA_MSC01_PCIIO_SIZE		0x00800000
32baf37f06SPaul Burton #define MALTA_MSC01_PCIIO_MAP		0x00000000
33baf37f06SPaul Burton #define MALTA_MSC01_UART0_BASE		(MALTA_MSC01_PCIIO_BASE + 0x3f8)
34ac12984dSGabor Juhos 
35*e0ada631SPaul Burton #define MALTA_ASCIIWORD			0x1f000410
36*e0ada631SPaul Burton #define MALTA_ASCIIPOS0			0x1f000418
37*e0ada631SPaul Burton #define MALTA_ASCIIPOS1			0x1f000420
38*e0ada631SPaul Burton #define MALTA_ASCIIPOS2			0x1f000428
39*e0ada631SPaul Burton #define MALTA_ASCIIPOS3			0x1f000430
40*e0ada631SPaul Burton #define MALTA_ASCIIPOS4			0x1f000438
41*e0ada631SPaul Burton #define MALTA_ASCIIPOS5			0x1f000440
42*e0ada631SPaul Burton #define MALTA_ASCIIPOS6			0x1f000448
43*e0ada631SPaul Burton #define MALTA_ASCIIPOS7			0x1f000450
44*e0ada631SPaul Burton 
4501564315SGabor Juhos #define MALTA_RESET_BASE		0x1f000500
4601564315SGabor Juhos #define GORESET				0x42
4701564315SGabor Juhos 
4852caee0fSGabor Juhos #define MALTA_FLASH_BASE		0x1fc00000
4952caee0fSGabor Juhos 
50baf37f06SPaul Burton #define MALTA_REVISION			0x1fc00010
51baf37f06SPaul Burton #define MALTA_REVISION_CORID_SHF	10
52baf37f06SPaul Burton #define MALTA_REVISION_CORID_MSK	(0x3f << MALTA_REVISION_CORID_SHF)
53baf37f06SPaul Burton #define MALTA_REVISION_CORID_CORE_LV		1
54baf37f06SPaul Burton #define MALTA_REVISION_CORID_CORE_FPGA6		14
55baf37f06SPaul Burton 
565a4dcfacSGabor Juhos #endif /* _MIPS_ASM_MALTA_H */
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