1 /* 2 * Copyright (C) 1994, 1995 Waldorf GmbH 3 * Copyright (C) 1994 - 2000, 06 Ralf Baechle 4 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 5 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 6 * Author: Maciej W. Rozycki <macro@mips.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 #ifndef _ASM_IO_H 11 #define _ASM_IO_H 12 13 #include <linux/bug.h> 14 #include <linux/compiler.h> 15 #include <linux/types.h> 16 17 #include <asm/addrspace.h> 18 #include <asm/byteorder.h> 19 #include <asm/cpu-features.h> 20 #include <asm/pgtable-bits.h> 21 #include <asm/processor.h> 22 #include <asm/string.h> 23 24 #include <ioremap.h> 25 #include <mangle-port.h> 26 #include <spaces.h> 27 28 /* 29 * Raw operations are never swapped in software. OTOH values that raw 30 * operations are working on may or may not have been swapped by the bus 31 * hardware. An example use would be for flash memory that's used for 32 * execute in place. 33 */ 34 # define __raw_ioswabb(a, x) (x) 35 # define __raw_ioswabw(a, x) (x) 36 # define __raw_ioswabl(a, x) (x) 37 # define __raw_ioswabq(a, x) (x) 38 # define ____raw_ioswabq(a, x) (x) 39 40 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 41 42 #define IO_SPACE_LIMIT 0xffff 43 44 /* 45 * On MIPS I/O ports are memory mapped, so we access them using normal 46 * load/store instructions. mips_io_port_base is the virtual address to 47 * which all ports are being mapped. For sake of efficiency some code 48 * assumes that this is an address that can be loaded with a single lui 49 * instruction, so the lower 16 bits must be zero. Should be true on 50 * on any sane architecture; generic code does not use this assumption. 51 */ 52 extern const unsigned long mips_io_port_base; 53 54 /* 55 * Gcc will generate code to load the value of mips_io_port_base after each 56 * function call which may be fairly wasteful in some cases. So we don't 57 * play quite by the book. We tell gcc mips_io_port_base is a long variable 58 * which solves the code generation issue. Now we need to violate the 59 * aliasing rules a little to make initialization possible and finally we 60 * will need the barrier() to fight side effects of the aliasing chat. 61 * This trickery will eventually collapse under gcc's optimizer. Oh well. 62 */ 63 static inline void set_io_port_base(unsigned long base) 64 { 65 * (unsigned long *) &mips_io_port_base = base; 66 barrier(); 67 } 68 69 /* 70 * virt_to_phys - map virtual addresses to physical 71 * @address: address to remap 72 * 73 * The returned physical address is the physical (CPU) mapping for 74 * the memory address given. It is only valid to use this function on 75 * addresses directly mapped or allocated via kmalloc. 76 * 77 * This function does not give bus mappings for DMA transfers. In 78 * almost all conceivable cases a device driver should not be using 79 * this function 80 */ 81 static inline unsigned long virt_to_phys(volatile const void *address) 82 { 83 unsigned long addr = (unsigned long)address; 84 85 /* this corresponds to kernel implementation of __pa() */ 86 #ifdef CONFIG_64BIT 87 if (addr < CKSEG0) 88 return XPHYSADDR(addr); 89 90 return CPHYSADDR(addr); 91 #else 92 return addr - PAGE_OFFSET + PHYS_OFFSET; 93 #endif 94 } 95 96 /* 97 * phys_to_virt - map physical address to virtual 98 * @address: address to remap 99 * 100 * The returned virtual address is a current CPU mapping for 101 * the memory address given. It is only valid to use this function on 102 * addresses that have a kernel mapping 103 * 104 * This function does not handle bus mappings for DMA transfers. In 105 * almost all conceivable cases a device driver should not be using 106 * this function 107 */ 108 static inline void *phys_to_virt(unsigned long address) 109 { 110 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); 111 } 112 113 /* 114 * ISA I/O bus memory addresses are 1:1 with the physical address. 115 */ 116 static inline unsigned long isa_virt_to_bus(volatile void *address) 117 { 118 return (unsigned long)address - PAGE_OFFSET; 119 } 120 121 static inline void *isa_bus_to_virt(unsigned long address) 122 { 123 return (void *)(address + PAGE_OFFSET); 124 } 125 126 #define isa_page_to_bus page_to_phys 127 128 /* 129 * However PCI ones are not necessarily 1:1 and therefore these interfaces 130 * are forbidden in portable PCI drivers. 131 * 132 * Allow them for x86 for legacy drivers, though. 133 */ 134 #define virt_to_bus virt_to_phys 135 #define bus_to_virt phys_to_virt 136 137 static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size, 138 unsigned long flags) 139 { 140 void __iomem *addr; 141 phys_addr_t phys_addr; 142 143 addr = plat_ioremap(offset, size, flags); 144 if (addr) 145 return addr; 146 147 phys_addr = fixup_bigphys_addr(offset, size); 148 return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr); 149 } 150 151 /* 152 * ioremap - map bus memory into CPU space 153 * @offset: bus address of the memory 154 * @size: size of the resource to map 155 * 156 * ioremap performs a platform specific sequence of operations to 157 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 158 * writew/writel functions and the other mmio helpers. The returned 159 * address is not guaranteed to be usable directly as a virtual 160 * address. 161 */ 162 #define ioremap(offset, size) \ 163 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 164 165 /* 166 * ioremap_nocache - map bus memory into CPU space 167 * @offset: bus address of the memory 168 * @size: size of the resource to map 169 * 170 * ioremap_nocache performs a platform specific sequence of operations to 171 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 172 * writew/writel functions and the other mmio helpers. The returned 173 * address is not guaranteed to be usable directly as a virtual 174 * address. 175 * 176 * This version of ioremap ensures that the memory is marked uncachable 177 * on the CPU as well as honouring existing caching rules from things like 178 * the PCI bus. Note that there are other caches and buffers on many 179 * busses. In particular driver authors should read up on PCI writes 180 * 181 * It's useful if some control registers are in such an area and 182 * write combining or read caching is not desirable: 183 */ 184 #define ioremap_nocache(offset, size) \ 185 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 186 #define ioremap_uc ioremap_nocache 187 188 /* 189 * ioremap_cachable - map bus memory into CPU space 190 * @offset: bus address of the memory 191 * @size: size of the resource to map 192 * 193 * ioremap_nocache performs a platform specific sequence of operations to 194 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 195 * writew/writel functions and the other mmio helpers. The returned 196 * address is not guaranteed to be usable directly as a virtual 197 * address. 198 * 199 * This version of ioremap ensures that the memory is marked cachable by 200 * the CPU. Also enables full write-combining. Useful for some 201 * memory-like regions on I/O busses. 202 */ 203 #define ioremap_cachable(offset, size) \ 204 __ioremap_mode((offset), (size), _page_cachable_default) 205 206 /* 207 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow 208 * requests a cachable mapping, ioremap_uncached_accelerated requests a 209 * mapping using the uncached accelerated mode which isn't supported on 210 * all processors. 211 */ 212 #define ioremap_cacheable_cow(offset, size) \ 213 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW) 214 #define ioremap_uncached_accelerated(offset, size) \ 215 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) 216 217 static inline void iounmap(const volatile void __iomem *addr) 218 { 219 plat_iounmap(addr); 220 } 221 222 #ifdef CONFIG_CPU_CAVIUM_OCTEON 223 #define war_octeon_io_reorder_wmb() wmb() 224 #else 225 #define war_octeon_io_reorder_wmb() do { } while (0) 226 #endif 227 228 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ 229 \ 230 static inline void pfx##write##bwlq(type val, \ 231 volatile void __iomem *mem) \ 232 { \ 233 volatile type *__mem; \ 234 type __val; \ 235 \ 236 war_octeon_io_reorder_wmb(); \ 237 \ 238 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 239 \ 240 __val = pfx##ioswab##bwlq(__mem, val); \ 241 \ 242 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 243 *__mem = __val; \ 244 else if (cpu_has_64bits) { \ 245 type __tmp; \ 246 \ 247 __asm__ __volatile__( \ 248 ".set arch=r4000" "\t\t# __writeq""\n\t" \ 249 "dsll32 %L0, %L0, 0" "\n\t" \ 250 "dsrl32 %L0, %L0, 0" "\n\t" \ 251 "dsll32 %M0, %M0, 0" "\n\t" \ 252 "or %L0, %L0, %M0" "\n\t" \ 253 "sd %L0, %2" "\n\t" \ 254 ".set mips0" "\n" \ 255 : "=r" (__tmp) \ 256 : "0" (__val), "m" (*__mem)); \ 257 } else \ 258 BUG(); \ 259 } \ 260 \ 261 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ 262 { \ 263 volatile type *__mem; \ 264 type __val; \ 265 \ 266 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 267 \ 268 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 269 __val = *__mem; \ 270 else if (cpu_has_64bits) { \ 271 __asm__ __volatile__( \ 272 ".set arch=r4000" "\t\t# __readq" "\n\t" \ 273 "ld %L0, %1" "\n\t" \ 274 "dsra32 %M0, %L0, 0" "\n\t" \ 275 "sll %L0, %L0, 0" "\n\t" \ 276 ".set mips0" "\n" \ 277 : "=r" (__val) \ 278 : "m" (*__mem)); \ 279 } else { \ 280 __val = 0; \ 281 BUG(); \ 282 } \ 283 \ 284 return pfx##ioswab##bwlq(__mem, __val); \ 285 } 286 287 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p) \ 288 \ 289 static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 290 { \ 291 volatile type *__addr; \ 292 type __val; \ 293 \ 294 war_octeon_io_reorder_wmb(); \ 295 \ 296 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 297 \ 298 __val = pfx##ioswab##bwlq(__addr, val); \ 299 \ 300 /* Really, we want this to be atomic */ \ 301 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 302 \ 303 *__addr = __val; \ 304 } \ 305 \ 306 static inline type pfx##in##bwlq##p(unsigned long port) \ 307 { \ 308 volatile type *__addr; \ 309 type __val; \ 310 \ 311 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 312 \ 313 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 314 \ 315 __val = *__addr; \ 316 \ 317 return pfx##ioswab##bwlq(__addr, __val); \ 318 } 319 320 #define __BUILD_MEMORY_PFX(bus, bwlq, type) \ 321 \ 322 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) 323 324 #define BUILDIO_MEM(bwlq, type) \ 325 \ 326 __BUILD_MEMORY_PFX(__raw_, bwlq, type) \ 327 __BUILD_MEMORY_PFX(, bwlq, type) \ 328 __BUILD_MEMORY_PFX(__mem_, bwlq, type) \ 329 330 BUILDIO_MEM(b, u8) 331 BUILDIO_MEM(w, u16) 332 BUILDIO_MEM(l, u32) 333 BUILDIO_MEM(q, u64) 334 335 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 336 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ) \ 337 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p) 338 339 #define BUILDIO_IOPORT(bwlq, type) \ 340 __BUILD_IOPORT_PFX(, bwlq, type) \ 341 __BUILD_IOPORT_PFX(__mem_, bwlq, type) 342 343 BUILDIO_IOPORT(b, u8) 344 BUILDIO_IOPORT(w, u16) 345 BUILDIO_IOPORT(l, u32) 346 #ifdef CONFIG_64BIT 347 BUILDIO_IOPORT(q, u64) 348 #endif 349 350 #define __BUILDIO(bwlq, type) \ 351 \ 352 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0) 353 354 __BUILDIO(q, u64) 355 356 #define readb_relaxed readb 357 #define readw_relaxed readw 358 #define readl_relaxed readl 359 #define readq_relaxed readq 360 361 #define writeb_relaxed writeb 362 #define writew_relaxed writew 363 #define writel_relaxed writel 364 #define writeq_relaxed writeq 365 366 #define readb_be(addr) \ 367 __raw_readb((__force unsigned *)(addr)) 368 #define readw_be(addr) \ 369 be16_to_cpu(__raw_readw((__force unsigned *)(addr))) 370 #define readl_be(addr) \ 371 be32_to_cpu(__raw_readl((__force unsigned *)(addr))) 372 #define readq_be(addr) \ 373 be64_to_cpu(__raw_readq((__force unsigned *)(addr))) 374 375 #define writeb_be(val, addr) \ 376 __raw_writeb((val), (__force unsigned *)(addr)) 377 #define writew_be(val, addr) \ 378 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) 379 #define writel_be(val, addr) \ 380 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) 381 #define writeq_be(val, addr) \ 382 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) 383 384 /* 385 * Some code tests for these symbols 386 */ 387 #define readq readq 388 #define writeq writeq 389 390 #define __BUILD_MEMORY_STRING(bwlq, type) \ 391 \ 392 static inline void writes##bwlq(volatile void __iomem *mem, \ 393 const void *addr, unsigned int count) \ 394 { \ 395 const volatile type *__addr = addr; \ 396 \ 397 while (count--) { \ 398 __mem_write##bwlq(*__addr, mem); \ 399 __addr++; \ 400 } \ 401 } \ 402 \ 403 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ 404 unsigned int count) \ 405 { \ 406 volatile type *__addr = addr; \ 407 \ 408 while (count--) { \ 409 *__addr = __mem_read##bwlq(mem); \ 410 __addr++; \ 411 } \ 412 } 413 414 #define __BUILD_IOPORT_STRING(bwlq, type) \ 415 \ 416 static inline void outs##bwlq(unsigned long port, const void *addr, \ 417 unsigned int count) \ 418 { \ 419 const volatile type *__addr = addr; \ 420 \ 421 while (count--) { \ 422 __mem_out##bwlq(*__addr, port); \ 423 __addr++; \ 424 } \ 425 } \ 426 \ 427 static inline void ins##bwlq(unsigned long port, void *addr, \ 428 unsigned int count) \ 429 { \ 430 volatile type *__addr = addr; \ 431 \ 432 while (count--) { \ 433 *__addr = __mem_in##bwlq(port); \ 434 __addr++; \ 435 } \ 436 } 437 438 #define BUILDSTRING(bwlq, type) \ 439 \ 440 __BUILD_MEMORY_STRING(bwlq, type) \ 441 __BUILD_IOPORT_STRING(bwlq, type) 442 443 BUILDSTRING(b, u8) 444 BUILDSTRING(w, u16) 445 BUILDSTRING(l, u32) 446 #ifdef CONFIG_64BIT 447 BUILDSTRING(q, u64) 448 #endif 449 450 451 #ifdef CONFIG_CPU_CAVIUM_OCTEON 452 #define mmiowb() wmb() 453 #else 454 /* Depends on MIPS II instruction set */ 455 #define mmiowb() asm volatile ("sync" ::: "memory") 456 #endif 457 458 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 459 { 460 memset((void __force *)addr, val, count); 461 } 462 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) 463 { 464 memcpy(dst, (void __force *)src, count); 465 } 466 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) 467 { 468 memcpy((void __force *)dst, src, count); 469 } 470 471 /* 472 * Read a 32-bit register that requires a 64-bit read cycle on the bus. 473 * Avoid interrupt mucking, just adjust the address for 4-byte access. 474 * Assume the addresses are 8-byte aligned. 475 */ 476 #ifdef __MIPSEB__ 477 #define __CSR_32_ADJUST 4 478 #else 479 #define __CSR_32_ADJUST 0 480 #endif 481 482 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) 483 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) 484 485 /* 486 * U-Boot specific 487 */ 488 #define sync() mmiowb() 489 490 #define MAP_NOCACHE (1) 491 #define MAP_WRCOMBINE (0) 492 #define MAP_WRBACK (0) 493 #define MAP_WRTHROUGH (0) 494 495 static inline void * 496 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) 497 { 498 if (flags == MAP_NOCACHE) 499 return ioremap(paddr, len); 500 501 return (void *)paddr; 502 } 503 504 /* 505 * Take down a mapping set up by map_physmem(). 506 */ 507 static inline void unmap_physmem(void *vaddr, unsigned long flags) 508 { 509 } 510 511 #define __BUILD_CLRBITS(bwlq, sfx, end, type) \ 512 \ 513 static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \ 514 { \ 515 type __val = __raw_read##bwlq(mem); \ 516 __val = end##_to_cpu(__val); \ 517 __val &= ~clr; \ 518 __val = cpu_to_##end(__val); \ 519 __raw_write##bwlq(__val, mem); \ 520 } 521 522 #define __BUILD_SETBITS(bwlq, sfx, end, type) \ 523 \ 524 static inline void setbits_##sfx(volatile void __iomem *mem, type set) \ 525 { \ 526 type __val = __raw_read##bwlq(mem); \ 527 __val = end##_to_cpu(__val); \ 528 __val |= set; \ 529 __val = cpu_to_##end(__val); \ 530 __raw_write##bwlq(__val, mem); \ 531 } 532 533 #define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \ 534 \ 535 static inline void clrsetbits_##sfx(volatile void __iomem *mem, \ 536 type clr, type set) \ 537 { \ 538 type __val = __raw_read##bwlq(mem); \ 539 __val = end##_to_cpu(__val); \ 540 __val &= ~clr; \ 541 __val |= set; \ 542 __val = cpu_to_##end(__val); \ 543 __raw_write##bwlq(__val, mem); \ 544 } 545 546 #define BUILD_CLRSETBITS(bwlq, sfx, end, type) \ 547 \ 548 __BUILD_CLRBITS(bwlq, sfx, end, type) \ 549 __BUILD_SETBITS(bwlq, sfx, end, type) \ 550 __BUILD_CLRSETBITS(bwlq, sfx, end, type) 551 552 #define __to_cpu(v) (v) 553 #define cpu_to__(v) (v) 554 555 BUILD_CLRSETBITS(b, 8, _, u8) 556 BUILD_CLRSETBITS(w, le16, le16, u16) 557 BUILD_CLRSETBITS(w, be16, be16, u16) 558 BUILD_CLRSETBITS(w, 16, _, u16) 559 BUILD_CLRSETBITS(l, le32, le32, u32) 560 BUILD_CLRSETBITS(l, be32, be32, u32) 561 BUILD_CLRSETBITS(l, 32, _, u32) 562 BUILD_CLRSETBITS(q, le64, le64, u64) 563 BUILD_CLRSETBITS(q, be64, be64, u64) 564 BUILD_CLRSETBITS(q, 64, _, u64) 565 566 #endif /* _ASM_IO_H */ 567