1 /* 2 * MIPS Coherence Manager (CM) Register Definitions 3 * 4 * Copyright (c) 2016 Imagination Technologies Ltd. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 #ifndef __MIPS_ASM_CM_H__ 9 #define __MIPS_ASM_CM_H__ 10 11 /* Global Control Register (GCR) offsets */ 12 #define GCR_BASE 0x0008 13 #define GCR_BASE_UPPER 0x000c 14 #define GCR_REV 0x0030 15 #define GCR_L2_CONFIG 0x0130 16 #define GCR_L2_TAG_ADDR 0x0600 17 #define GCR_L2_TAG_ADDR_UPPER 0x0604 18 #define GCR_L2_TAG_STATE 0x0608 19 #define GCR_L2_TAG_STATE_UPPER 0x060c 20 #define GCR_L2_DATA 0x0610 21 #define GCR_L2_DATA_UPPER 0x0614 22 23 /* GCR_REV CM versions */ 24 #define GCR_REV_CM3 0x0800 25 26 /* GCR_L2_CONFIG fields */ 27 #define GCR_L2_CONFIG_ASSOC_SHIFT 0 28 #define GCR_L2_CONFIG_ASSOC_BITS 8 29 #define GCR_L2_CONFIG_LINESZ_SHIFT 8 30 #define GCR_L2_CONFIG_LINESZ_BITS 4 31 #define GCR_L2_CONFIG_SETSZ_SHIFT 12 32 #define GCR_L2_CONFIG_SETSZ_BITS 4 33 #define GCR_L2_CONFIG_BYPASS (1 << 20) 34 35 #ifndef __ASSEMBLY__ 36 37 #include <asm/io.h> 38 39 static inline void *mips_cm_base(void) 40 { 41 return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); 42 } 43 44 static inline unsigned long mips_cm_l2_line_size(void) 45 { 46 unsigned long l2conf, line_sz; 47 48 l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG); 49 50 line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT; 51 line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); 52 return line_sz ? (2 << line_sz) : 0; 53 } 54 55 #endif /* !__ASSEMBLY__ */ 56 57 #endif /* __MIPS_ASM_CM_H__ */ 58