1b2b135d9SPaul Burton /* 2b2b135d9SPaul Burton * MIPS Coherence Manager (CM) Register Definitions 3b2b135d9SPaul Burton * 4b2b135d9SPaul Burton * Copyright (c) 2016 Imagination Technologies Ltd. 5b2b135d9SPaul Burton * 6b2b135d9SPaul Burton * SPDX-License-Identifier: GPL-2.0+ 7b2b135d9SPaul Burton */ 8b2b135d9SPaul Burton #ifndef __MIPS_ASM_CM_H__ 9b2b135d9SPaul Burton #define __MIPS_ASM_CM_H__ 10b2b135d9SPaul Burton 11b2b135d9SPaul Burton /* Global Control Register (GCR) offsets */ 12b2b135d9SPaul Burton #define GCR_BASE 0x0008 13b2b135d9SPaul Burton #define GCR_BASE_UPPER 0x000c 14b2b135d9SPaul Burton #define GCR_REV 0x0030 15*4baa0ab6SPaul Burton #define GCR_L2_CONFIG 0x0130 16*4baa0ab6SPaul Burton #define GCR_L2_TAG_ADDR 0x0600 17*4baa0ab6SPaul Burton #define GCR_L2_TAG_ADDR_UPPER 0x0604 18*4baa0ab6SPaul Burton #define GCR_L2_TAG_STATE 0x0608 19*4baa0ab6SPaul Burton #define GCR_L2_TAG_STATE_UPPER 0x060c 20*4baa0ab6SPaul Burton #define GCR_L2_DATA 0x0610 21*4baa0ab6SPaul Burton #define GCR_L2_DATA_UPPER 0x0614 22b2b135d9SPaul Burton 23b2b135d9SPaul Burton /* GCR_REV CM versions */ 24b2b135d9SPaul Burton #define GCR_REV_CM3 0x0800 25b2b135d9SPaul Burton 26*4baa0ab6SPaul Burton /* GCR_L2_CONFIG fields */ 27*4baa0ab6SPaul Burton #define GCR_L2_CONFIG_ASSOC_SHIFT 0 28*4baa0ab6SPaul Burton #define GCR_L2_CONFIG_ASSOC_BITS 8 29*4baa0ab6SPaul Burton #define GCR_L2_CONFIG_LINESZ_SHIFT 8 30*4baa0ab6SPaul Burton #define GCR_L2_CONFIG_LINESZ_BITS 4 31*4baa0ab6SPaul Burton #define GCR_L2_CONFIG_SETSZ_SHIFT 12 32*4baa0ab6SPaul Burton #define GCR_L2_CONFIG_SETSZ_BITS 4 33*4baa0ab6SPaul Burton #define GCR_L2_CONFIG_BYPASS (1 << 20) 34*4baa0ab6SPaul Burton 35*4baa0ab6SPaul Burton #ifndef __ASSEMBLY__ 36*4baa0ab6SPaul Burton 37*4baa0ab6SPaul Burton #include <asm/io.h> 38*4baa0ab6SPaul Burton 39*4baa0ab6SPaul Burton static inline void *mips_cm_base(void) 40*4baa0ab6SPaul Burton { 41*4baa0ab6SPaul Burton return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); 42*4baa0ab6SPaul Burton } 43*4baa0ab6SPaul Burton 44*4baa0ab6SPaul Burton static inline unsigned long mips_cm_l2_line_size(void) 45*4baa0ab6SPaul Burton { 46*4baa0ab6SPaul Burton unsigned long l2conf, line_sz; 47*4baa0ab6SPaul Burton 48*4baa0ab6SPaul Burton l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG); 49*4baa0ab6SPaul Burton 50*4baa0ab6SPaul Burton line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT; 51*4baa0ab6SPaul Burton line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); 52*4baa0ab6SPaul Burton return line_sz ? (2 << line_sz) : 0; 53*4baa0ab6SPaul Burton } 54*4baa0ab6SPaul Burton 55*4baa0ab6SPaul Burton #endif /* !__ASSEMBLY__ */ 56*4baa0ab6SPaul Burton 57b2b135d9SPaul Burton #endif /* __MIPS_ASM_CM_H__ */ 58