1819833afSPeter Tyser /* 2819833afSPeter Tyser * Cache operations for the cache instruction. 3819833afSPeter Tyser * 4819833afSPeter Tyser * This file is subject to the terms and conditions of the GNU General Public 5819833afSPeter Tyser * License. See the file "COPYING" in the main directory of this archive 6819833afSPeter Tyser * for more details. 7819833afSPeter Tyser * 8819833afSPeter Tyser * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle 9819833afSPeter Tyser * (C) Copyright 1999 Silicon Graphics, Inc. 10819833afSPeter Tyser */ 11819833afSPeter Tyser #ifndef __ASM_CACHEOPS_H 12819833afSPeter Tyser #define __ASM_CACHEOPS_H 13819833afSPeter Tyser 14*2b8bcc5aSPaul Burton #ifndef __ASSEMBLY__ 15*2b8bcc5aSPaul Burton 16*2b8bcc5aSPaul Burton static inline void mips_cache(int op, const volatile void *addr) 17*2b8bcc5aSPaul Burton { 18*2b8bcc5aSPaul Burton #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE 19*2b8bcc5aSPaul Burton __builtin_mips_cache(op, addr); 20*2b8bcc5aSPaul Burton #else 21*2b8bcc5aSPaul Burton __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr)) 22*2b8bcc5aSPaul Burton #endif 23*2b8bcc5aSPaul Burton } 24*2b8bcc5aSPaul Burton 25*2b8bcc5aSPaul Burton #endif /* !__ASSEMBLY__ */ 26*2b8bcc5aSPaul Burton 27819833afSPeter Tyser /* 28819833afSPeter Tyser * Cache Operations available on all MIPS processors with R4000-style caches 29819833afSPeter Tyser */ 30cb0a6a1eSZhi-zhou Zhang #define INDEX_INVALIDATE_I 0x00 31cb0a6a1eSZhi-zhou Zhang #define INDEX_WRITEBACK_INV_D 0x01 32cb0a6a1eSZhi-zhou Zhang #define INDEX_LOAD_TAG_I 0x04 33cb0a6a1eSZhi-zhou Zhang #define INDEX_LOAD_TAG_D 0x05 34cb0a6a1eSZhi-zhou Zhang #define INDEX_STORE_TAG_I 0x08 35cb0a6a1eSZhi-zhou Zhang #define INDEX_STORE_TAG_D 0x09 36819833afSPeter Tyser #if defined(CONFIG_CPU_LOONGSON2) 37cb0a6a1eSZhi-zhou Zhang #define HIT_INVALIDATE_I 0x00 38819833afSPeter Tyser #else 39cb0a6a1eSZhi-zhou Zhang #define HIT_INVALIDATE_I 0x10 40819833afSPeter Tyser #endif 41cb0a6a1eSZhi-zhou Zhang #define HIT_INVALIDATE_D 0x11 42cb0a6a1eSZhi-zhou Zhang #define HIT_WRITEBACK_INV_D 0x15 43819833afSPeter Tyser 44819833afSPeter Tyser /* 45819833afSPeter Tyser * R4000-specific cacheops 46819833afSPeter Tyser */ 47cb0a6a1eSZhi-zhou Zhang #define CREATE_DIRTY_EXCL_D 0x0d 48cb0a6a1eSZhi-zhou Zhang #define FILL 0x14 49cb0a6a1eSZhi-zhou Zhang #define HIT_WRITEBACK_I 0x18 50cb0a6a1eSZhi-zhou Zhang #define HIT_WRITEBACK_D 0x19 51819833afSPeter Tyser 52819833afSPeter Tyser /* 53819833afSPeter Tyser * R4000SC and R4400SC-specific cacheops 54819833afSPeter Tyser */ 55cb0a6a1eSZhi-zhou Zhang #define INDEX_INVALIDATE_SI 0x02 56cb0a6a1eSZhi-zhou Zhang #define INDEX_WRITEBACK_INV_SD 0x03 57cb0a6a1eSZhi-zhou Zhang #define INDEX_LOAD_TAG_SI 0x06 58cb0a6a1eSZhi-zhou Zhang #define INDEX_LOAD_TAG_SD 0x07 59cb0a6a1eSZhi-zhou Zhang #define INDEX_STORE_TAG_SI 0x0A 60cb0a6a1eSZhi-zhou Zhang #define INDEX_STORE_TAG_SD 0x0B 61cb0a6a1eSZhi-zhou Zhang #define CREATE_DIRTY_EXCL_SD 0x0f 62cb0a6a1eSZhi-zhou Zhang #define HIT_INVALIDATE_SI 0x12 63cb0a6a1eSZhi-zhou Zhang #define HIT_INVALIDATE_SD 0x13 64cb0a6a1eSZhi-zhou Zhang #define HIT_WRITEBACK_INV_SD 0x17 65cb0a6a1eSZhi-zhou Zhang #define HIT_WRITEBACK_SD 0x1b 66cb0a6a1eSZhi-zhou Zhang #define HIT_SET_VIRTUAL_SI 0x1e 67cb0a6a1eSZhi-zhou Zhang #define HIT_SET_VIRTUAL_SD 0x1f 68819833afSPeter Tyser 69819833afSPeter Tyser /* 70819833afSPeter Tyser * R5000-specific cacheops 71819833afSPeter Tyser */ 72cb0a6a1eSZhi-zhou Zhang #define R5K_PAGE_INVALIDATE_S 0x17 73819833afSPeter Tyser 74819833afSPeter Tyser /* 75819833afSPeter Tyser * RM7000-specific cacheops 76819833afSPeter Tyser */ 77cb0a6a1eSZhi-zhou Zhang #define PAGE_INVALIDATE_T 0x16 78819833afSPeter Tyser 79819833afSPeter Tyser /* 80819833afSPeter Tyser * R10000-specific cacheops 81819833afSPeter Tyser * 82819833afSPeter Tyser * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 83819833afSPeter Tyser * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 84819833afSPeter Tyser */ 85cb0a6a1eSZhi-zhou Zhang #define INDEX_WRITEBACK_INV_S 0x03 86cb0a6a1eSZhi-zhou Zhang #define INDEX_LOAD_TAG_S 0x07 87cb0a6a1eSZhi-zhou Zhang #define INDEX_STORE_TAG_S 0x0B 88cb0a6a1eSZhi-zhou Zhang #define HIT_INVALIDATE_S 0x13 89cb0a6a1eSZhi-zhou Zhang #define CACHE_BARRIER 0x14 90cb0a6a1eSZhi-zhou Zhang #define HIT_WRITEBACK_INV_S 0x17 91cb0a6a1eSZhi-zhou Zhang #define INDEX_LOAD_DATA_I 0x18 92cb0a6a1eSZhi-zhou Zhang #define INDEX_LOAD_DATA_D 0x19 93cb0a6a1eSZhi-zhou Zhang #define INDEX_LOAD_DATA_S 0x1b 94cb0a6a1eSZhi-zhou Zhang #define INDEX_STORE_DATA_I 0x1c 95cb0a6a1eSZhi-zhou Zhang #define INDEX_STORE_DATA_D 0x1d 96cb0a6a1eSZhi-zhou Zhang #define INDEX_STORE_DATA_S 0x1f 97819833afSPeter Tyser 98819833afSPeter Tyser #endif /* __ASM_CACHEOPS_H */ 99