172d4dd41SAnton Staaf /* 272d4dd41SAnton Staaf * Copyright (c) 2011 The Chromium OS Authors. 372d4dd41SAnton Staaf * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 572d4dd41SAnton Staaf */ 672d4dd41SAnton Staaf 772d4dd41SAnton Staaf #ifndef __MIPS_CACHE_H__ 872d4dd41SAnton Staaf #define __MIPS_CACHE_H__ 972d4dd41SAnton Staaf 10f53830e7SDaniel Schwierzeck #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT 11f53830e7SDaniel Schwierzeck #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 12f53830e7SDaniel Schwierzeck 13f53830e7SDaniel Schwierzeck #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) 1472d4dd41SAnton Staaf 15*37228621SPaul Burton /* 16*37228621SPaul Burton * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for 17*37228621SPaul Burton * DMA buffer alignment. Satisfy those drivers by providing it as a synonym 18*37228621SPaul Burton * of ARCH_DMA_MINALIGN for now. 19*37228621SPaul Burton */ 20*37228621SPaul Burton #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN 21*37228621SPaul Burton 2272d4dd41SAnton Staaf #endif /* __MIPS_CACHE_H__ */ 23