172d4dd41SAnton Staaf /* 272d4dd41SAnton Staaf * Copyright (c) 2011 The Chromium OS Authors. 372d4dd41SAnton Staaf * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 572d4dd41SAnton Staaf */ 672d4dd41SAnton Staaf 772d4dd41SAnton Staaf #ifndef __MIPS_CACHE_H__ 872d4dd41SAnton Staaf #define __MIPS_CACHE_H__ 972d4dd41SAnton Staaf 1072d4dd41SAnton Staaf /* 1172d4dd41SAnton Staaf * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use 1272d4dd41SAnton Staaf * that as a default for aligning DMA buffers unless the board config has 1372d4dd41SAnton Staaf * specified another cache line size. 1472d4dd41SAnton Staaf */ 1572d4dd41SAnton Staaf #ifdef CONFIG_SYS_CACHELINE_SIZE 1672d4dd41SAnton Staaf #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 1772d4dd41SAnton Staaf #else 1872d4dd41SAnton Staaf #define ARCH_DMA_MINALIGN 128 1972d4dd41SAnton Staaf #endif 2072d4dd41SAnton Staaf 2172d4dd41SAnton Staaf #endif /* __MIPS_CACHE_H__ */ 22