xref: /rk3399_rockchip-uboot/arch/mips/dts/pic32mzda.dtsi (revision 7e8f270292ebacb25f366181f2022c819e5c7586)
1be961fa1SPurna Chandra Mandal/*
2be961fa1SPurna Chandra Mandal * Copyright 2015 Microchip Technology, Inc.
3be961fa1SPurna Chandra Mandal * Purna Chandra Mandal, <purna.mandal@microchip.com>
4be961fa1SPurna Chandra Mandal *
5be961fa1SPurna Chandra Mandal * SPDX-License-Identifier:	GPL-2.0+
6be961fa1SPurna Chandra Mandal */
7be961fa1SPurna Chandra Mandal
8be961fa1SPurna Chandra Mandal#include <dt-bindings/interrupt-controller/irq.h>
9be961fa1SPurna Chandra Mandal#include <dt-bindings/clock/microchip,clock.h>
10be961fa1SPurna Chandra Mandal#include <dt-bindings/gpio/gpio.h>
11be961fa1SPurna Chandra Mandal#include "skeleton.dtsi"
12be961fa1SPurna Chandra Mandal
13be961fa1SPurna Chandra Mandal/ {
14be961fa1SPurna Chandra Mandal	compatible = "microchip,pic32mzda", "microchip,pic32mz";
15be961fa1SPurna Chandra Mandal
16be961fa1SPurna Chandra Mandal	aliases {
17be961fa1SPurna Chandra Mandal		gpio0 = &gpioA;
18be961fa1SPurna Chandra Mandal		gpio1 = &gpioB;
19be961fa1SPurna Chandra Mandal		gpio2 = &gpioC;
20be961fa1SPurna Chandra Mandal		gpio3 = &gpioD;
21be961fa1SPurna Chandra Mandal		gpio4 = &gpioE;
22be961fa1SPurna Chandra Mandal		gpio5 = &gpioF;
23be961fa1SPurna Chandra Mandal		gpio6 = &gpioG;
24be961fa1SPurna Chandra Mandal		gpio7 = &gpioH;
25be961fa1SPurna Chandra Mandal		gpio8 = &gpioJ;
26be961fa1SPurna Chandra Mandal		gpio9 = &gpioK;
27be961fa1SPurna Chandra Mandal	};
28be961fa1SPurna Chandra Mandal
29be961fa1SPurna Chandra Mandal	cpus {
30be961fa1SPurna Chandra Mandal		cpu@0 {
31be961fa1SPurna Chandra Mandal			compatible = "mips,mips14kc";
32be961fa1SPurna Chandra Mandal		};
33be961fa1SPurna Chandra Mandal	};
34be961fa1SPurna Chandra Mandal
35be961fa1SPurna Chandra Mandal	clock: clk@1f801200 {
36be961fa1SPurna Chandra Mandal		compatible = "microchip,pic32mzda-clk";
37be961fa1SPurna Chandra Mandal		reg = <0x1f801200 0x1000>;
38be961fa1SPurna Chandra Mandal		#clock-cells = <1>;
39be961fa1SPurna Chandra Mandal	};
40be961fa1SPurna Chandra Mandal
41be961fa1SPurna Chandra Mandal	uart1: serial@1f822000 {
42be961fa1SPurna Chandra Mandal		compatible = "microchip,pic32mzda-uart";
43be961fa1SPurna Chandra Mandal		reg = <0x1f822000 0x50>;
44be961fa1SPurna Chandra Mandal		interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
45be961fa1SPurna Chandra Mandal		status = "disabled";
46be961fa1SPurna Chandra Mandal		clocks = <&clock PB2CLK>;
47be961fa1SPurna Chandra Mandal	};
48be961fa1SPurna Chandra Mandal
49be961fa1SPurna Chandra Mandal	uart2: serial@1f822200 {
50be961fa1SPurna Chandra Mandal		compatible = "microchip,pic32mzda-uart";
51be961fa1SPurna Chandra Mandal		reg = <0x1f822200 0x50>;
52be961fa1SPurna Chandra Mandal		interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
53be961fa1SPurna Chandra Mandal		clocks = <&clock PB2CLK>;
54be961fa1SPurna Chandra Mandal		status = "disabled";
55be961fa1SPurna Chandra Mandal	};
56be961fa1SPurna Chandra Mandal
57be961fa1SPurna Chandra Mandal	uart6: serial@1f822a00 {
58be961fa1SPurna Chandra Mandal		compatible = "microchip,pic32mzda-uart";
59be961fa1SPurna Chandra Mandal		reg = <0x1f822a00 0x50>;
60be961fa1SPurna Chandra Mandal		interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
61be961fa1SPurna Chandra Mandal		clocks = <&clock PB2CLK>;
62be961fa1SPurna Chandra Mandal		status = "disabled";
63be961fa1SPurna Chandra Mandal	};
64be961fa1SPurna Chandra Mandal
65be961fa1SPurna Chandra Mandal	evic: interrupt-controller@1f810000 {
66be961fa1SPurna Chandra Mandal		compatible = "microchip,pic32mzda-evic";
67be961fa1SPurna Chandra Mandal		interrupt-controller;
68be961fa1SPurna Chandra Mandal		#interrupt-cells = <2>;
69be961fa1SPurna Chandra Mandal		reg = <0x1f810000 0x1000>;
70be961fa1SPurna Chandra Mandal	};
71be961fa1SPurna Chandra Mandal
72be961fa1SPurna Chandra Mandal	pinctrl: pinctrl@1f801400 {
73be961fa1SPurna Chandra Mandal		compatible = "microchip,pic32mzda-pinctrl";
74be961fa1SPurna Chandra Mandal		reg = <0x1f801400 0x100>, /* in  */
75be961fa1SPurna Chandra Mandal		      <0x1f801500 0x200>, /* out */
76be961fa1SPurna Chandra Mandal		      <0x1f860000 0xa00>; /* port */
77be961fa1SPurna Chandra Mandal		reg-names = "ppsin","ppsout","port";
78be961fa1SPurna Chandra Mandal		status = "disabled";
79be961fa1SPurna Chandra Mandal
80be961fa1SPurna Chandra Mandal		ranges = <0 0x1f860000 0xa00>;
81be961fa1SPurna Chandra Mandal		#address-cells = <1>;
82be961fa1SPurna Chandra Mandal		#size-cells = <1>;
83be961fa1SPurna Chandra Mandal		gpioA: gpio0@0 {
84be961fa1SPurna Chandra Mandal			compatible = "microchip,pic32mzda-gpio";
85be961fa1SPurna Chandra Mandal			reg = <0x000 0x48>;
86be961fa1SPurna Chandra Mandal			gpio-controller;
87be961fa1SPurna Chandra Mandal			#gpio-cells = <2>;
88be961fa1SPurna Chandra Mandal		};
89be961fa1SPurna Chandra Mandal
90be961fa1SPurna Chandra Mandal		gpioB: gpio1@100 {
91be961fa1SPurna Chandra Mandal			compatible = "microchip,pic32mzda-gpio";
92be961fa1SPurna Chandra Mandal			reg = <0x100 0x48>;
93be961fa1SPurna Chandra Mandal			gpio-controller;
94be961fa1SPurna Chandra Mandal			#gpio-cells = <2>;
95be961fa1SPurna Chandra Mandal		};
96be961fa1SPurna Chandra Mandal
97be961fa1SPurna Chandra Mandal		gpioC: gpio2@200 {
98be961fa1SPurna Chandra Mandal			compatible = "microchip,pic32mzda-gpio";
99be961fa1SPurna Chandra Mandal			reg = <0x200 0x48>;
100be961fa1SPurna Chandra Mandal			gpio-controller;
101be961fa1SPurna Chandra Mandal			#gpio-cells = <2>;
102be961fa1SPurna Chandra Mandal		};
103be961fa1SPurna Chandra Mandal
104be961fa1SPurna Chandra Mandal		gpioD: gpio3@300 {
105be961fa1SPurna Chandra Mandal			compatible = "microchip,pic32mzda-gpio";
106be961fa1SPurna Chandra Mandal			reg = <0x300 0x48>;
107be961fa1SPurna Chandra Mandal			gpio-controller;
108be961fa1SPurna Chandra Mandal			#gpio-cells = <2>;
109be961fa1SPurna Chandra Mandal		};
110be961fa1SPurna Chandra Mandal
111be961fa1SPurna Chandra Mandal		gpioE: gpio4@400 {
112be961fa1SPurna Chandra Mandal			compatible = "microchip,pic32mzda-gpio";
113be961fa1SPurna Chandra Mandal			reg = <0x400 0x48>;
114be961fa1SPurna Chandra Mandal			gpio-controller;
115be961fa1SPurna Chandra Mandal			#gpio-cells = <2>;
116be961fa1SPurna Chandra Mandal		};
117be961fa1SPurna Chandra Mandal
118be961fa1SPurna Chandra Mandal		gpioF: gpio5@500 {
119be961fa1SPurna Chandra Mandal			compatible = "microchip,pic32mzda-gpio";
120be961fa1SPurna Chandra Mandal			reg = <0x500 0x48>;
121be961fa1SPurna Chandra Mandal			gpio-controller;
122be961fa1SPurna Chandra Mandal			#gpio-cells = <2>;
123be961fa1SPurna Chandra Mandal		};
124be961fa1SPurna Chandra Mandal
125be961fa1SPurna Chandra Mandal		gpioG: gpio6@600 {
126be961fa1SPurna Chandra Mandal			compatible = "microchip,pic32mzda-gpio";
127be961fa1SPurna Chandra Mandal			reg = <0x600 0x48>;
128be961fa1SPurna Chandra Mandal			gpio-controller;
129be961fa1SPurna Chandra Mandal			#gpio-cells = <2>;
130be961fa1SPurna Chandra Mandal		};
131be961fa1SPurna Chandra Mandal
132be961fa1SPurna Chandra Mandal		gpioH: gpio7@700 {
133be961fa1SPurna Chandra Mandal			compatible = "microchip,pic32mzda-gpio";
134be961fa1SPurna Chandra Mandal			reg = <0x700 0x48>;
135be961fa1SPurna Chandra Mandal			gpio-controller;
136be961fa1SPurna Chandra Mandal			#gpio-cells = <2>;
137be961fa1SPurna Chandra Mandal		};
138be961fa1SPurna Chandra Mandal
139be961fa1SPurna Chandra Mandal		gpioJ: gpio8@800 {
140be961fa1SPurna Chandra Mandal			compatible = "microchip,pic32mzda-gpio";
141be961fa1SPurna Chandra Mandal			reg = <0x800 0x48>;
142be961fa1SPurna Chandra Mandal			gpio-controller;
143be961fa1SPurna Chandra Mandal			#gpio-cells = <2>;
144be961fa1SPurna Chandra Mandal		};
145be961fa1SPurna Chandra Mandal
146be961fa1SPurna Chandra Mandal		gpioK: gpio9@900 {
147be961fa1SPurna Chandra Mandal			compatible = "microchip,pic32mzda-gpio";
148be961fa1SPurna Chandra Mandal			reg = <0x900 0x48>;
149be961fa1SPurna Chandra Mandal			gpio-controller;
150be961fa1SPurna Chandra Mandal			#gpio-cells = <2>;
151be961fa1SPurna Chandra Mandal		};
152be961fa1SPurna Chandra Mandal	};
153c76eb72cSPurna Chandra Mandal
154c76eb72cSPurna Chandra Mandal	sdhci: sdhci@1f8ec000 {
155c76eb72cSPurna Chandra Mandal		compatible = "microchip,pic32mzda-sdhci";
156c76eb72cSPurna Chandra Mandal		reg = <0x1f8ec000 0x100>;
157c76eb72cSPurna Chandra Mandal		interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
158c76eb72cSPurna Chandra Mandal		clocks = <&clock REF4CLK>, <&clock PB5CLK>;
159c76eb72cSPurna Chandra Mandal		clock-names = "base_clk", "sys_clk";
160c76eb72cSPurna Chandra Mandal		clock-freq-min-max = <25000000>,<25000000>;
161c76eb72cSPurna Chandra Mandal		bus-width = <4>;
162c76eb72cSPurna Chandra Mandal		status = "disabled";
163c76eb72cSPurna Chandra Mandal	};
1647d514a74SPurna Chandra Mandal
1657d514a74SPurna Chandra Mandal	ethernet: ethernet@1f882000 {
1667d514a74SPurna Chandra Mandal		compatible = "microchip,pic32mzda-eth";
1677d514a74SPurna Chandra Mandal		reg = <0x1f882000 0x1000>;
1687d514a74SPurna Chandra Mandal		interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
1697d514a74SPurna Chandra Mandal		clocks = <&clock PB5CLK>;
1707d514a74SPurna Chandra Mandal		status = "disabled";
1717d514a74SPurna Chandra Mandal		#address-cells = <1>;
1727d514a74SPurna Chandra Mandal		#size-cells = <0>;
1737d514a74SPurna Chandra Mandal	};
174*ac7eef71SPurna Chandra Mandal
175*ac7eef71SPurna Chandra Mandal	usb: musb@1f8e3000 {
176*ac7eef71SPurna Chandra Mandal		compatible = "microchip,pic32mzda-usb";
177*ac7eef71SPurna Chandra Mandal		reg = <0x1f8e3000 0x1000>,
178*ac7eef71SPurna Chandra Mandal		      <0x1f884000 0x1000>;
179*ac7eef71SPurna Chandra Mandal		reg-names = "mc", "control";
180*ac7eef71SPurna Chandra Mandal		interrupts = <132 IRQ_TYPE_EDGE_RISING>,
181*ac7eef71SPurna Chandra Mandal			     <133 IRQ_TYPE_LEVEL_HIGH>;
182*ac7eef71SPurna Chandra Mandal		clocks = <&clock PB5CLK>;
183*ac7eef71SPurna Chandra Mandal		clock-names = "usb_clk";
184*ac7eef71SPurna Chandra Mandal		status = "disabled";
185*ac7eef71SPurna Chandra Mandal	};
186be961fa1SPurna Chandra Mandal};
187