xref: /rk3399_rockchip-uboot/arch/mips/dts/ar934x.dtsi (revision 08ca213acadef61748dc62d48b0f5c4bed8b8c2d)

/*
 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include "skeleton.dtsi"

/ {
	compatible = "qca,ar934x";

	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "mips,mips74Kc";
			reg = <0>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		xtal: xtal {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-output-names = "xtal";
		};
	};

	ahb {
		compatible = "simple-bus";
		ranges;

		#address-cells = <1>;
		#size-cells = <1>;

		apb {
			compatible = "simple-bus";
			ranges;

			#address-cells = <1>;
			#size-cells = <1>;

			ehci0: ehci@1b000100 {
				compatible = "generic-ehci";
				reg = <0x1b000100 0x100>;

				status = "disabled";
			};

			uart0: uart@18020000 {
				compatible = "ns16550";
				reg = <0x18020000 0x20>;
				reg-shift = <2>;

				status = "disabled";
			};

			gmac0: eth@0x19000000 {
				compatible = "qca,ag934x-mac";
				reg = <0x19000000 0x200>;
				phy = <&phy0>;
				phy-mode = "rgmii";

				status = "disabled";

				mdio {
					#address-cells = <1>;
					#size-cells = <0>;
					phy0: ethernet-phy@0 {
						reg = <0>;
					};
				};
			};

			gmac1: eth@0x1a000000 {
				compatible = "qca,ag934x-mac";
				reg = <0x1a000000 0x200>;
				phy = <&phy1>;
				phy-mode = "rgmii";

				status = "disabled";

				mdio {
					#address-cells = <1>;
					#size-cells = <0>;
					phy1: ethernet-phy@0 {
						reg = <0>;
					};
				};
			};
		};

		spi0: spi@1f000000 {
			compatible = "qca,ar7100-spi";
			reg = <0x1f000000 0x10>;

			status = "disabled";

			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};