xref: /rk3399_rockchip-uboot/arch/mips/dts/ap143.dts (revision 08ca213acadef61748dc62d48b0f5c4bed8b8c2d)
1*a2277cc3SWills Wang/*
2*a2277cc3SWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
3*a2277cc3SWills Wang *
4*a2277cc3SWills Wang * SPDX-License-Identifier: GPL-2.0+
5*a2277cc3SWills Wang */
6*a2277cc3SWills Wang
7*a2277cc3SWills Wang/dts-v1/;
8*a2277cc3SWills Wang#include "qca953x.dtsi"
9*a2277cc3SWills Wang
10*a2277cc3SWills Wang/ {
11*a2277cc3SWills Wang	model = "AP143 Reference Board";
12*a2277cc3SWills Wang	compatible = "qca,ap143", "qca,qca953x";
13*a2277cc3SWills Wang
14*a2277cc3SWills Wang	aliases {
15*a2277cc3SWills Wang		spi0 = &spi0;
16*a2277cc3SWills Wang		serial0 = &uart0;
17*a2277cc3SWills Wang	};
18*a2277cc3SWills Wang
19*a2277cc3SWills Wang	chosen {
20*a2277cc3SWills Wang		stdout-path = "serial0:115200n8";
21*a2277cc3SWills Wang	};
22*a2277cc3SWills Wang};
23*a2277cc3SWills Wang
24*a2277cc3SWills Wang&xtal {
25*a2277cc3SWills Wang	clock-frequency = <25000000>;
26*a2277cc3SWills Wang};
27*a2277cc3SWills Wang
28*a2277cc3SWills Wang&uart0 {
29*a2277cc3SWills Wang	status = "okay";
30*a2277cc3SWills Wang};
31*a2277cc3SWills Wang
32*a2277cc3SWills Wang&spi0 {
33*a2277cc3SWills Wang	spi-max-frequency = <25000000>;
34*a2277cc3SWills Wang	status = "okay";
35*a2277cc3SWills Wang	spi-flash@0 {
36*a2277cc3SWills Wang		#address-cells = <1>;
37*a2277cc3SWills Wang		#size-cells = <1>;
38*a2277cc3SWills Wang		compatible = "spi-flash";
39*a2277cc3SWills Wang		memory-map = <0x9f000000 0x00800000>;
40*a2277cc3SWills Wang		spi-max-frequency = <25000000>;
41*a2277cc3SWills Wang		reg = <0>;
42*a2277cc3SWills Wang	};
43*a2277cc3SWills Wang};
44