1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2 9 default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 24config TARGET_MALTA 25 bool "Support malta" 26 select SUPPORTS_BIG_ENDIAN 27 select SUPPORTS_LITTLE_ENDIAN 28 select SUPPORTS_CPU_MIPS32_R1 29 select SUPPORTS_CPU_MIPS32_R2 30 select SWAP_IO_SPACE 31 32config TARGET_VCT 33 bool "Support vct" 34 select SUPPORTS_BIG_ENDIAN 35 select SUPPORTS_CPU_MIPS32_R1 36 select SUPPORTS_CPU_MIPS32_R2 37 select SYS_MIPS_CACHE_INIT_RAM_LOAD 38 39config TARGET_DBAU1X00 40 bool "Support dbau1x00" 41 select SUPPORTS_BIG_ENDIAN 42 select SUPPORTS_LITTLE_ENDIAN 43 select SUPPORTS_CPU_MIPS32_R1 44 select SUPPORTS_CPU_MIPS32_R2 45 select SYS_MIPS_CACHE_INIT_RAM_LOAD 46 select MIPS_TUNE_4KC 47 48config TARGET_PB1X00 49 bool "Support pb1x00" 50 select SUPPORTS_LITTLE_ENDIAN 51 select SUPPORTS_CPU_MIPS32_R1 52 select SUPPORTS_CPU_MIPS32_R2 53 select SYS_MIPS_CACHE_INIT_RAM_LOAD 54 select MIPS_TUNE_4KC 55 56endchoice 57 58source "board/dbau1x00/Kconfig" 59source "board/imgtec/malta/Kconfig" 60source "board/micronas/vct/Kconfig" 61source "board/pb1x00/Kconfig" 62source "board/qemu-mips/Kconfig" 63 64if MIPS 65 66choice 67 prompt "Endianness selection" 68 help 69 Some MIPS boards can be configured for either little or big endian 70 byte order. These modes require different U-Boot images. In general there 71 is one preferred byteorder for a particular system but some systems are 72 just as commonly used in the one or the other endianness. 73 74config SYS_BIG_ENDIAN 75 bool "Big endian" 76 depends on SUPPORTS_BIG_ENDIAN 77 78config SYS_LITTLE_ENDIAN 79 bool "Little endian" 80 depends on SUPPORTS_LITTLE_ENDIAN 81 82endchoice 83 84choice 85 prompt "CPU selection" 86 default CPU_MIPS32_R2 87 88config CPU_MIPS32_R1 89 bool "MIPS32 Release 1" 90 depends on SUPPORTS_CPU_MIPS32_R1 91 select 32BIT 92 help 93 Choose this option to build an U-Boot for release 1 or later of the 94 MIPS32 architecture. 95 96config CPU_MIPS32_R2 97 bool "MIPS32 Release 2" 98 depends on SUPPORTS_CPU_MIPS32_R2 99 select 32BIT 100 help 101 Choose this option to build an U-Boot for release 2 or later of the 102 MIPS32 architecture. 103 104config CPU_MIPS64_R1 105 bool "MIPS64 Release 1" 106 depends on SUPPORTS_CPU_MIPS64_R1 107 select 64BIT 108 help 109 Choose this option to build a kernel for release 1 or later of the 110 MIPS64 architecture. 111 112config CPU_MIPS64_R2 113 bool "MIPS64 Release 2" 114 depends on SUPPORTS_CPU_MIPS64_R2 115 select 64BIT 116 help 117 Choose this option to build a kernel for release 2 or later of the 118 MIPS64 architecture. 119 120endchoice 121 122menu "OS boot interface" 123 124config MIPS_BOOT_CMDLINE_LEGACY 125 bool "Hand over legacy command line to Linux kernel" 126 default y 127 help 128 Enable this option if you want U-Boot to hand over the Yamon-style 129 command line to the kernel. All bootargs will be prepared as argc/argv 130 compatible list. The argument count (argc) is stored in register $a0. 131 The address of the argument list (argv) is stored in register $a1. 132 133config MIPS_BOOT_ENV_LEGACY 134 bool "Hand over legacy environment to Linux kernel" 135 default y 136 help 137 Enable this option if you want U-Boot to hand over the Yamon-style 138 environment to the kernel. Information like memory size, initrd 139 address and size will be prepared as zero-terminated key/value list. 140 The address of the enviroment is stored in register $a2. 141 142config MIPS_BOOT_FDT 143 bool "Hand over a flattened device tree to Linux kernel" 144 default n 145 help 146 Enable this option if you want U-Boot to hand over a flattened 147 device tree to the kernel. According to UHI register $a0 will be set 148 to -2 and the FDT address is stored in $a1. 149 150endmenu 151 152config SUPPORTS_BIG_ENDIAN 153 bool 154 155config SUPPORTS_LITTLE_ENDIAN 156 bool 157 158config SUPPORTS_CPU_MIPS32_R1 159 bool 160 161config SUPPORTS_CPU_MIPS32_R2 162 bool 163 164config SUPPORTS_CPU_MIPS64_R1 165 bool 166 167config SUPPORTS_CPU_MIPS64_R2 168 bool 169 170config CPU_MIPS32 171 bool 172 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 173 174config CPU_MIPS64 175 bool 176 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 177 178config MIPS_TUNE_4KC 179 bool 180 181config MIPS_TUNE_14KC 182 bool 183 184config MIPS_TUNE_24KC 185 bool 186 187config 32BIT 188 bool 189 190config 64BIT 191 bool 192 193config SWAP_IO_SPACE 194 bool 195 196config SYS_MIPS_CACHE_INIT_RAM_LOAD 197 bool 198 199endif 200 201endmenu 202