1dd84058dSMasahiro Yamadamenu "MIPS architecture" 2dd84058dSMasahiro Yamada depends on MIPS 3dd84058dSMasahiro Yamada 4dd84058dSMasahiro Yamadaconfig SYS_ARCH 5dd84058dSMasahiro Yamada default "mips" 6dd84058dSMasahiro Yamada 7b9863b6dSDaniel Schwierzeckconfig SYS_CPU 820286cdfSPaul Burton default "mips32" if CPU_MIPS32 920286cdfSPaul Burton default "mips64" if CPU_MIPS64 10b9863b6dSDaniel Schwierzeck 11dd84058dSMasahiro Yamadachoice 12dd84058dSMasahiro Yamada prompt "Target select" 13a26cd049SJoe Hershberger optional 14dd84058dSMasahiro Yamada 15dd84058dSMasahiro Yamadaconfig TARGET_QEMU_MIPS 16dd84058dSMasahiro Yamada bool "Support qemu-mips" 170e1dc345SDaniel Schwierzeck select SUPPORTS_BIG_ENDIAN 180e1dc345SDaniel Schwierzeck select SUPPORTS_LITTLE_ENDIAN 1902611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R1 2002611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R2 21aa45f75eSDaniel Schwierzeck select SUPPORTS_CPU_MIPS64_R1 22aa45f75eSDaniel Schwierzeck select SUPPORTS_CPU_MIPS64_R2 23dd84058dSMasahiro Yamada 24dd84058dSMasahiro Yamadaconfig TARGET_MALTA 25dd84058dSMasahiro Yamada bool "Support malta" 266242aa13SPaul Burton select DM 276242aa13SPaul Burton select DM_SERIAL 2805e34255SPaul Burton select DYNAMIC_IO_PORT_BASE 29*566ce04dSPaul Burton select MIPS_CM 30*566ce04dSPaul Burton select MIPS_L2_CACHE 316242aa13SPaul Burton select OF_CONTROL 326242aa13SPaul Burton select OF_ISA_BUS 330e1dc345SDaniel Schwierzeck select SUPPORTS_BIG_ENDIAN 340e1dc345SDaniel Schwierzeck select SUPPORTS_LITTLE_ENDIAN 3502611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R1 3602611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R2 3740ba13c9SPaul Burton select SUPPORTS_CPU_MIPS32_R6 380f832b9cSPaul Burton select SUPPORTS_CPU_MIPS64_R1 390f832b9cSPaul Burton select SUPPORTS_CPU_MIPS64_R2 400f832b9cSPaul Burton select SUPPORTS_CPU_MIPS64_R6 419d638eeaSDaniel Schwierzeck select SWAP_IO_SPACE 42f53830e7SDaniel Schwierzeck select MIPS_L1_CACHE_SHIFT_6 43dd84058dSMasahiro Yamada 44dd84058dSMasahiro Yamadaconfig TARGET_VCT 45dd84058dSMasahiro Yamada bool "Support vct" 460e1dc345SDaniel Schwierzeck select SUPPORTS_BIG_ENDIAN 4702611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R1 4802611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R2 49dd7c7200SPaul Burton select SYS_MIPS_CACHE_INIT_RAM_LOAD 50dd84058dSMasahiro Yamada 51dd84058dSMasahiro Yamadaconfig TARGET_DBAU1X00 52dd84058dSMasahiro Yamada bool "Support dbau1x00" 530e1dc345SDaniel Schwierzeck select SUPPORTS_BIG_ENDIAN 540e1dc345SDaniel Schwierzeck select SUPPORTS_LITTLE_ENDIAN 5502611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R1 5602611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R2 57dd7c7200SPaul Burton select SYS_MIPS_CACHE_INIT_RAM_LOAD 580315a289SDaniel Schwierzeck select MIPS_TUNE_4KC 59dd84058dSMasahiro Yamada 60dd84058dSMasahiro Yamadaconfig TARGET_PB1X00 61dd84058dSMasahiro Yamada bool "Support pb1x00" 620e1dc345SDaniel Schwierzeck select SUPPORTS_LITTLE_ENDIAN 6302611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R1 6402611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R2 65dd7c7200SPaul Burton select SYS_MIPS_CACHE_INIT_RAM_LOAD 660315a289SDaniel Schwierzeck select MIPS_TUNE_4KC 67dd84058dSMasahiro Yamada 681d3d0f1fSWills Wangconfig ARCH_ATH79 691d3d0f1fSWills Wang bool "Support QCA/Atheros ath79" 701d3d0f1fSWills Wang select OF_CONTROL 711d3d0f1fSWills Wang select DM 721d3d0f1fSWills Wang 7332c1a6eeSPurna Chandra Mandalconfig MACH_PIC32 7432c1a6eeSPurna Chandra Mandal bool "Support Microchip PIC32" 7532c1a6eeSPurna Chandra Mandal select OF_CONTROL 7632c1a6eeSPurna Chandra Mandal select DM 7732c1a6eeSPurna Chandra Mandal 78ebf2b9e3SZubair Lutfullah Kakakhelconfig TARGET_XILFPGA 79ebf2b9e3SZubair Lutfullah Kakakhel bool "Support Imagination Xilfpga" 80ebf2b9e3SZubair Lutfullah Kakakhel select OF_CONTROL 81ebf2b9e3SZubair Lutfullah Kakakhel select DM 82ebf2b9e3SZubair Lutfullah Kakakhel select DM_SERIAL 83ebf2b9e3SZubair Lutfullah Kakakhel select DM_GPIO 84ebf2b9e3SZubair Lutfullah Kakakhel select DM_ETH 85ebf2b9e3SZubair Lutfullah Kakakhel select SUPPORTS_LITTLE_ENDIAN 86ebf2b9e3SZubair Lutfullah Kakakhel select SUPPORTS_CPU_MIPS32_R1 87ebf2b9e3SZubair Lutfullah Kakakhel select SUPPORTS_CPU_MIPS32_R2 88ebf2b9e3SZubair Lutfullah Kakakhel select MIPS_L1_CACHE_SHIFT_4 89ebf2b9e3SZubair Lutfullah Kakakhel help 90ebf2b9e3SZubair Lutfullah Kakakhel This supports IMGTEC MIPSfpga platform 91ebf2b9e3SZubair Lutfullah Kakakhel 92dd84058dSMasahiro Yamadaendchoice 93dd84058dSMasahiro Yamada 94dd84058dSMasahiro Yamadasource "board/dbau1x00/Kconfig" 95dd84058dSMasahiro Yamadasource "board/imgtec/malta/Kconfig" 96ebf2b9e3SZubair Lutfullah Kakakhelsource "board/imgtec/xilfpga/Kconfig" 97dd84058dSMasahiro Yamadasource "board/micronas/vct/Kconfig" 98dd84058dSMasahiro Yamadasource "board/pb1x00/Kconfig" 99dd84058dSMasahiro Yamadasource "board/qemu-mips/Kconfig" 1001d3d0f1fSWills Wangsource "arch/mips/mach-ath79/Kconfig" 10132c1a6eeSPurna Chandra Mandalsource "arch/mips/mach-pic32/Kconfig" 102dd84058dSMasahiro Yamada 1030e1dc345SDaniel Schwierzeckif MIPS 1040e1dc345SDaniel Schwierzeck 1050e1dc345SDaniel Schwierzeckchoice 1060e1dc345SDaniel Schwierzeck prompt "Endianness selection" 1070e1dc345SDaniel Schwierzeck help 1080e1dc345SDaniel Schwierzeck Some MIPS boards can be configured for either little or big endian 1090e1dc345SDaniel Schwierzeck byte order. These modes require different U-Boot images. In general there 1100e1dc345SDaniel Schwierzeck is one preferred byteorder for a particular system but some systems are 1110e1dc345SDaniel Schwierzeck just as commonly used in the one or the other endianness. 1120e1dc345SDaniel Schwierzeck 1130e1dc345SDaniel Schwierzeckconfig SYS_BIG_ENDIAN 1140e1dc345SDaniel Schwierzeck bool "Big endian" 1150e1dc345SDaniel Schwierzeck depends on SUPPORTS_BIG_ENDIAN 1160e1dc345SDaniel Schwierzeck 1170e1dc345SDaniel Schwierzeckconfig SYS_LITTLE_ENDIAN 1180e1dc345SDaniel Schwierzeck bool "Little endian" 1190e1dc345SDaniel Schwierzeck depends on SUPPORTS_LITTLE_ENDIAN 1200e1dc345SDaniel Schwierzeck 1210e1dc345SDaniel Schwierzeckendchoice 1220e1dc345SDaniel Schwierzeck 12302611cbbSDaniel Schwierzeckchoice 12402611cbbSDaniel Schwierzeck prompt "CPU selection" 12502611cbbSDaniel Schwierzeck default CPU_MIPS32_R2 12602611cbbSDaniel Schwierzeck 12702611cbbSDaniel Schwierzeckconfig CPU_MIPS32_R1 12802611cbbSDaniel Schwierzeck bool "MIPS32 Release 1" 12902611cbbSDaniel Schwierzeck depends on SUPPORTS_CPU_MIPS32_R1 13002611cbbSDaniel Schwierzeck select 32BIT 13102611cbbSDaniel Schwierzeck help 132c52ebea1SPaul Burton Choose this option to build an U-Boot for release 1 through 5 of the 13302611cbbSDaniel Schwierzeck MIPS32 architecture. 13402611cbbSDaniel Schwierzeck 13502611cbbSDaniel Schwierzeckconfig CPU_MIPS32_R2 13602611cbbSDaniel Schwierzeck bool "MIPS32 Release 2" 13702611cbbSDaniel Schwierzeck depends on SUPPORTS_CPU_MIPS32_R2 13802611cbbSDaniel Schwierzeck select 32BIT 13902611cbbSDaniel Schwierzeck help 140c52ebea1SPaul Burton Choose this option to build an U-Boot for release 2 through 5 of the 141c52ebea1SPaul Burton MIPS32 architecture. 142c52ebea1SPaul Burton 143c52ebea1SPaul Burtonconfig CPU_MIPS32_R6 144c52ebea1SPaul Burton bool "MIPS32 Release 6" 145c52ebea1SPaul Burton depends on SUPPORTS_CPU_MIPS32_R6 146c52ebea1SPaul Burton select 32BIT 147c52ebea1SPaul Burton help 148c52ebea1SPaul Burton Choose this option to build an U-Boot for release 6 or later of the 14902611cbbSDaniel Schwierzeck MIPS32 architecture. 15002611cbbSDaniel Schwierzeck 15102611cbbSDaniel Schwierzeckconfig CPU_MIPS64_R1 15202611cbbSDaniel Schwierzeck bool "MIPS64 Release 1" 15302611cbbSDaniel Schwierzeck depends on SUPPORTS_CPU_MIPS64_R1 15402611cbbSDaniel Schwierzeck select 64BIT 15502611cbbSDaniel Schwierzeck help 156c52ebea1SPaul Burton Choose this option to build a kernel for release 1 through 5 of the 15702611cbbSDaniel Schwierzeck MIPS64 architecture. 15802611cbbSDaniel Schwierzeck 15902611cbbSDaniel Schwierzeckconfig CPU_MIPS64_R2 16002611cbbSDaniel Schwierzeck bool "MIPS64 Release 2" 16102611cbbSDaniel Schwierzeck depends on SUPPORTS_CPU_MIPS64_R2 16202611cbbSDaniel Schwierzeck select 64BIT 16302611cbbSDaniel Schwierzeck help 164c52ebea1SPaul Burton Choose this option to build a kernel for release 2 through 5 of the 165c52ebea1SPaul Burton MIPS64 architecture. 166c52ebea1SPaul Burton 167c52ebea1SPaul Burtonconfig CPU_MIPS64_R6 168c52ebea1SPaul Burton bool "MIPS64 Release 6" 169c52ebea1SPaul Burton depends on SUPPORTS_CPU_MIPS64_R6 170c52ebea1SPaul Burton select 64BIT 171c52ebea1SPaul Burton help 172c52ebea1SPaul Burton Choose this option to build a kernel for release 6 or later of the 17302611cbbSDaniel Schwierzeck MIPS64 architecture. 17402611cbbSDaniel Schwierzeck 17502611cbbSDaniel Schwierzeckendchoice 17602611cbbSDaniel Schwierzeck 17725fc664fSDaniel Schwierzeckmenu "OS boot interface" 17825fc664fSDaniel Schwierzeck 17925fc664fSDaniel Schwierzeckconfig MIPS_BOOT_CMDLINE_LEGACY 18025fc664fSDaniel Schwierzeck bool "Hand over legacy command line to Linux kernel" 18125fc664fSDaniel Schwierzeck default y 18225fc664fSDaniel Schwierzeck help 18325fc664fSDaniel Schwierzeck Enable this option if you want U-Boot to hand over the Yamon-style 18425fc664fSDaniel Schwierzeck command line to the kernel. All bootargs will be prepared as argc/argv 18525fc664fSDaniel Schwierzeck compatible list. The argument count (argc) is stored in register $a0. 18625fc664fSDaniel Schwierzeck The address of the argument list (argv) is stored in register $a1. 18725fc664fSDaniel Schwierzeck 188ca65e585SDaniel Schwierzeckconfig MIPS_BOOT_ENV_LEGACY 189ca65e585SDaniel Schwierzeck bool "Hand over legacy environment to Linux kernel" 190ca65e585SDaniel Schwierzeck default y 191ca65e585SDaniel Schwierzeck help 192ca65e585SDaniel Schwierzeck Enable this option if you want U-Boot to hand over the Yamon-style 193ca65e585SDaniel Schwierzeck environment to the kernel. Information like memory size, initrd 194ca65e585SDaniel Schwierzeck address and size will be prepared as zero-terminated key/value list. 1951cc0a9f4SRobert P. J. Day The address of the environment is stored in register $a2. 196ca65e585SDaniel Schwierzeck 1975002d8ccSDaniel Schwierzeckconfig MIPS_BOOT_FDT 19890b1c9faSDaniel Schwierzeck bool "Hand over a flattened device tree to Linux kernel" 1995002d8ccSDaniel Schwierzeck default n 2005002d8ccSDaniel Schwierzeck help 2015002d8ccSDaniel Schwierzeck Enable this option if you want U-Boot to hand over a flattened 20290b1c9faSDaniel Schwierzeck device tree to the kernel. According to UHI register $a0 will be set 20390b1c9faSDaniel Schwierzeck to -2 and the FDT address is stored in $a1. 2045002d8ccSDaniel Schwierzeck 20525fc664fSDaniel Schwierzeckendmenu 20625fc664fSDaniel Schwierzeck 2070e1dc345SDaniel Schwierzeckconfig SUPPORTS_BIG_ENDIAN 2080e1dc345SDaniel Schwierzeck bool 2090e1dc345SDaniel Schwierzeck 2100e1dc345SDaniel Schwierzeckconfig SUPPORTS_LITTLE_ENDIAN 2110e1dc345SDaniel Schwierzeck bool 2120e1dc345SDaniel Schwierzeck 21302611cbbSDaniel Schwierzeckconfig SUPPORTS_CPU_MIPS32_R1 21402611cbbSDaniel Schwierzeck bool 21502611cbbSDaniel Schwierzeck 21602611cbbSDaniel Schwierzeckconfig SUPPORTS_CPU_MIPS32_R2 21702611cbbSDaniel Schwierzeck bool 21802611cbbSDaniel Schwierzeck 219c52ebea1SPaul Burtonconfig SUPPORTS_CPU_MIPS32_R6 220c52ebea1SPaul Burton bool 221c52ebea1SPaul Burton 22202611cbbSDaniel Schwierzeckconfig SUPPORTS_CPU_MIPS64_R1 22302611cbbSDaniel Schwierzeck bool 22402611cbbSDaniel Schwierzeck 22502611cbbSDaniel Schwierzeckconfig SUPPORTS_CPU_MIPS64_R2 22602611cbbSDaniel Schwierzeck bool 22702611cbbSDaniel Schwierzeck 228c52ebea1SPaul Burtonconfig SUPPORTS_CPU_MIPS64_R6 229c52ebea1SPaul Burton bool 230c52ebea1SPaul Burton 231c57dafb5SDaniel Schwierzeckconfig CPU_MIPS32 232c57dafb5SDaniel Schwierzeck bool 233c52ebea1SPaul Burton default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 234c57dafb5SDaniel Schwierzeck 235c57dafb5SDaniel Schwierzeckconfig CPU_MIPS64 236c57dafb5SDaniel Schwierzeck bool 237c52ebea1SPaul Burton default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 238c57dafb5SDaniel Schwierzeck 2390315a289SDaniel Schwierzeckconfig MIPS_TUNE_4KC 2400315a289SDaniel Schwierzeck bool 2410315a289SDaniel Schwierzeck 2420315a289SDaniel Schwierzeckconfig MIPS_TUNE_14KC 2430315a289SDaniel Schwierzeck bool 2440315a289SDaniel Schwierzeck 2450315a289SDaniel Schwierzeckconfig MIPS_TUNE_24KC 2460315a289SDaniel Schwierzeck bool 2470315a289SDaniel Schwierzeck 2485f9cc363SDaniel Schwierzeckconfig MIPS_TUNE_34KC 2495f9cc363SDaniel Schwierzeck bool 2505f9cc363SDaniel Schwierzeck 2510a0a958bSMarek Vasutconfig MIPS_TUNE_74KC 2520a0a958bSMarek Vasut bool 2530a0a958bSMarek Vasut 25402611cbbSDaniel Schwierzeckconfig 32BIT 25502611cbbSDaniel Schwierzeck bool 25602611cbbSDaniel Schwierzeck 25702611cbbSDaniel Schwierzeckconfig 64BIT 25802611cbbSDaniel Schwierzeck bool 25902611cbbSDaniel Schwierzeck 2609d638eeaSDaniel Schwierzeckconfig SWAP_IO_SPACE 2619d638eeaSDaniel Schwierzeck bool 2629d638eeaSDaniel Schwierzeck 263dd7c7200SPaul Burtonconfig SYS_MIPS_CACHE_INIT_RAM_LOAD 264dd7c7200SPaul Burton bool 265dd7c7200SPaul Burton 266ace3be4fSPaul Burtonconfig SYS_DCACHE_SIZE 267ace3be4fSPaul Burton int 268ace3be4fSPaul Burton default 0 269ace3be4fSPaul Burton help 270ace3be4fSPaul Burton The total size of the L1 Dcache, if known at compile time. 271ace3be4fSPaul Burton 27237228621SPaul Burtonconfig SYS_DCACHE_LINE_SIZE 2734b7b0a0fSPaul Burton int 27437228621SPaul Burton default 0 27537228621SPaul Burton help 27637228621SPaul Burton The size of L1 Dcache lines, if known at compile time. 27737228621SPaul Burton 278ace3be4fSPaul Burtonconfig SYS_ICACHE_SIZE 279ace3be4fSPaul Burton int 280ace3be4fSPaul Burton default 0 281ace3be4fSPaul Burton help 282ace3be4fSPaul Burton The total size of the L1 ICache, if known at compile time. 283ace3be4fSPaul Burton 28437228621SPaul Burtonconfig SYS_ICACHE_LINE_SIZE 285ace3be4fSPaul Burton int 286ace3be4fSPaul Burton default 0 287ace3be4fSPaul Burton help 28837228621SPaul Burton The size of L1 Icache lines, if known at compile time. 289ace3be4fSPaul Burton 290ace3be4fSPaul Burtonconfig SYS_CACHE_SIZE_AUTO 291ace3be4fSPaul Burton def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 29237228621SPaul Burton SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 293ace3be4fSPaul Burton help 294ace3be4fSPaul Burton Select this (or let it be auto-selected by not defining any cache 295ace3be4fSPaul Burton sizes) in order to allow U-Boot to automatically detect the sizes 296ace3be4fSPaul Burton of caches at runtime. This has a small cost in code size & runtime 297ace3be4fSPaul Burton so if you know the cache configuration for your system at compile 298ace3be4fSPaul Burton time it would be beneficial to configure it. 299ace3be4fSPaul Burton 300f53830e7SDaniel Schwierzeckconfig MIPS_L1_CACHE_SHIFT_4 301f53830e7SDaniel Schwierzeck bool 302f53830e7SDaniel Schwierzeck 303f53830e7SDaniel Schwierzeckconfig MIPS_L1_CACHE_SHIFT_5 304f53830e7SDaniel Schwierzeck bool 305f53830e7SDaniel Schwierzeck 306f53830e7SDaniel Schwierzeckconfig MIPS_L1_CACHE_SHIFT_6 307f53830e7SDaniel Schwierzeck bool 308f53830e7SDaniel Schwierzeck 309f53830e7SDaniel Schwierzeckconfig MIPS_L1_CACHE_SHIFT_7 310f53830e7SDaniel Schwierzeck bool 311f53830e7SDaniel Schwierzeck 312f53830e7SDaniel Schwierzeckconfig MIPS_L1_CACHE_SHIFT 313f53830e7SDaniel Schwierzeck int 314f53830e7SDaniel Schwierzeck default "7" if MIPS_L1_CACHE_SHIFT_7 315f53830e7SDaniel Schwierzeck default "6" if MIPS_L1_CACHE_SHIFT_6 316f53830e7SDaniel Schwierzeck default "5" if MIPS_L1_CACHE_SHIFT_5 317f53830e7SDaniel Schwierzeck default "4" if MIPS_L1_CACHE_SHIFT_4 318f53830e7SDaniel Schwierzeck default "5" 319f53830e7SDaniel Schwierzeck 3204baa0ab6SPaul Burtonconfig MIPS_L2_CACHE 3214baa0ab6SPaul Burton bool 3224baa0ab6SPaul Burton help 3234baa0ab6SPaul Burton Select this if your system includes an L2 cache and you want U-Boot 3244baa0ab6SPaul Burton to initialise & maintain it. 3254baa0ab6SPaul Burton 32605e34255SPaul Burtonconfig DYNAMIC_IO_PORT_BASE 32705e34255SPaul Burton bool 32805e34255SPaul Burton 329b2b135d9SPaul Burtonconfig MIPS_CM 330b2b135d9SPaul Burton bool 331b2b135d9SPaul Burton help 332b2b135d9SPaul Burton Select this if your system contains a MIPS Coherence Manager and you 333b2b135d9SPaul Burton wish U-Boot to configure it or make use of it to retrieve system 334b2b135d9SPaul Burton information such as cache configuration. 335b2b135d9SPaul Burton 336b2b135d9SPaul Burtonconfig MIPS_CM_BASE 337b2b135d9SPaul Burton hex 338b2b135d9SPaul Burton default 0x1fbf8000 339b2b135d9SPaul Burton help 340b2b135d9SPaul Burton The physical base address at which to map the MIPS Coherence Manager 341b2b135d9SPaul Burton Global Configuration Registers (GCRs). This should be set such that 342b2b135d9SPaul Burton the GCRs occupy a region of the physical address space which is 343b2b135d9SPaul Burton otherwise unused, or at minimum that software doesn't need to access. 344b2b135d9SPaul Burton 3450e1dc345SDaniel Schwierzeckendif 3460e1dc345SDaniel Schwierzeck 347dd84058dSMasahiro Yamadaendmenu 348