xref: /rk3399_rockchip-uboot/arch/microblaze/include/asm/cache.h (revision ee729afde3a4782e1ef57962afd13fb7208f5cb8)
1*ee729afdSAnton Staaf /*
2*ee729afdSAnton Staaf  * Copyright (c) 2011 The Chromium OS Authors.
3*ee729afdSAnton Staaf  * See file CREDITS for list of people who contributed to this
4*ee729afdSAnton Staaf  * project.
5*ee729afdSAnton Staaf  *
6*ee729afdSAnton Staaf  * This program is free software; you can redistribute it and/or
7*ee729afdSAnton Staaf  * modify it under the terms of the GNU General Public License as
8*ee729afdSAnton Staaf  * published by the Free Software Foundation; either version 2 of
9*ee729afdSAnton Staaf  * the License, or (at your option) any later version.
10*ee729afdSAnton Staaf  *
11*ee729afdSAnton Staaf  * This program is distributed in the hope that it will be useful,
12*ee729afdSAnton Staaf  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13*ee729afdSAnton Staaf  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14*ee729afdSAnton Staaf  * GNU General Public License for more details.
15*ee729afdSAnton Staaf  *
16*ee729afdSAnton Staaf  * You should have received a copy of the GNU General Public License
17*ee729afdSAnton Staaf  * along with this program; if not, write to the Free Software
18*ee729afdSAnton Staaf  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19*ee729afdSAnton Staaf  * MA 02111-1307 USA
20*ee729afdSAnton Staaf  */
21*ee729afdSAnton Staaf 
22*ee729afdSAnton Staaf #ifndef __MICROBLAZE_CACHE_H__
23*ee729afdSAnton Staaf #define __MICROBLAZE_CACHE_H__
24*ee729afdSAnton Staaf 
25*ee729afdSAnton Staaf /*
26*ee729afdSAnton Staaf  * The microblaze can have either a 4 or 16 byte cacheline depending on whether
27*ee729afdSAnton Staaf  * you are using OPB(4) or CacheLink(16).  If the board config has not specified
28*ee729afdSAnton Staaf  * a cacheline size we assume the larger value of 16 bytes for DMA buffer
29*ee729afdSAnton Staaf  * alignment.
30*ee729afdSAnton Staaf  */
31*ee729afdSAnton Staaf #ifdef CONFIG_SYS_CACHELINE_SIZE
32*ee729afdSAnton Staaf #define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
33*ee729afdSAnton Staaf #else
34*ee729afdSAnton Staaf #define ARCH_DMA_MINALIGN	16
35*ee729afdSAnton Staaf #endif
36*ee729afdSAnton Staaf 
37*ee729afdSAnton Staaf #endif /* __MICROBLAZE_CACHE_H__ */
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