xref: /rk3399_rockchip-uboot/arch/microblaze/cpu/interrupts.c (revision 9aa65cab73e4873f3e94c6df3d0efd99f3bc9926)
1 /*
2  * (C) Copyright 2007 Michal Simek
3  * (C) Copyright 2004 Atmark Techno, Inc.
4  *
5  * Michal  SIMEK <monstr@monstr.eu>
6  * Yasushi SHOJI <yashi@atmark-techno.com>
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #include <common.h>
12 #include <command.h>
13 #include <fdtdec.h>
14 #include <malloc.h>
15 #include <asm/microblaze_intc.h>
16 #include <asm/asm.h>
17 
18 DECLARE_GLOBAL_DATA_PTR;
19 
20 void enable_interrupts(void)
21 {
22 	debug("Enable interrupts for the whole CPU\n");
23 	MSRSET(0x2);
24 }
25 
26 int disable_interrupts(void)
27 {
28 	unsigned int msr;
29 
30 	MFS(msr, rmsr);
31 	MSRCLR(0x2);
32 	return (msr & 0x2) != 0;
33 }
34 
35 static struct irq_action *vecs;
36 static u32 irq_no;
37 
38 /* mapping structure to interrupt controller */
39 microblaze_intc_t *intc;
40 
41 /* default handler */
42 static void def_hdlr(void)
43 {
44 	puts("def_hdlr\n");
45 }
46 
47 static void enable_one_interrupt(int irq)
48 {
49 	int mask;
50 	int offset = 1;
51 
52 	offset <<= irq;
53 	mask = intc->ier;
54 	intc->ier = (mask | offset);
55 
56 	debug("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
57 	      intc->ier);
58 	debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
59 	      intc->iar, intc->mer);
60 }
61 
62 static void disable_one_interrupt(int irq)
63 {
64 	int mask;
65 	int offset = 1;
66 
67 	offset <<= irq;
68 	mask = intc->ier;
69 	intc->ier = (mask & ~offset);
70 
71 	debug("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
72 	      intc->ier);
73 	debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
74 	      intc->iar, intc->mer);
75 }
76 
77 int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg)
78 {
79 	struct irq_action *act;
80 
81 	/* irq out of range */
82 	if ((irq < 0) || (irq > irq_no)) {
83 		puts("IRQ out of range\n");
84 		return -1;
85 	}
86 	act = &vecs[irq];
87 	if (hdlr) {		/* enable */
88 		act->handler = hdlr;
89 		act->arg = arg;
90 		act->count = 0;
91 		enable_one_interrupt(irq);
92 		return 0;
93 	}
94 
95 	/* Disable */
96 	act->handler = (interrupt_handler_t *)def_hdlr;
97 	act->arg = (void *)irq;
98 	disable_one_interrupt(irq);
99 	return 1;
100 }
101 
102 /* initialization interrupt controller - hardware */
103 static void intc_init(void)
104 {
105 	intc->mer = 0;
106 	intc->ier = 0;
107 	intc->iar = 0xFFFFFFFF;
108 	/* XIntc_Start - hw_interrupt enable and all interrupt enable */
109 	intc->mer = 0x3;
110 
111 	debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
112 	      intc->iar, intc->mer);
113 }
114 
115 int interrupt_init(void)
116 {
117 	int i;
118 
119 #ifdef CONFIG_OF_CONTROL
120 	const void *blob = gd->fdt_blob;
121 	int node = 0;
122 
123 	debug("INTC: Initialization\n");
124 
125 	node = fdt_node_offset_by_compatible(blob, node,
126 				"xlnx,xps-intc-1.00.a");
127 	if (node != -1) {
128 		fdt_addr_t base = fdtdec_get_addr(blob, node, "reg");
129 		if (base == FDT_ADDR_T_NONE)
130 			return -1;
131 
132 		debug("INTC: Base addr %lx\n", base);
133 		intc = (microblaze_intc_t *)base;
134 		irq_no = fdtdec_get_int(blob, node, "xlnx,num-intr-inputs", 0);
135 		debug("INTC: IRQ NO %x\n", irq_no);
136 	} else {
137 		return node;
138 	}
139 #else
140 #if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
141 	intc = (microblaze_intc_t *)CONFIG_SYS_INTC_0_ADDR;
142 	irq_no = CONFIG_SYS_INTC_0_NUM;
143 #endif
144 #endif
145 	if (irq_no) {
146 		vecs = calloc(1, sizeof(struct irq_action) * irq_no);
147 		if (vecs == NULL) {
148 			puts("Interrupt vector allocation failed\n");
149 			return -1;
150 		}
151 
152 		/* initialize irq list */
153 		for (i = 0; i < irq_no; i++) {
154 			vecs[i].handler = (interrupt_handler_t *)def_hdlr;
155 			vecs[i].arg = (void *)i;
156 			vecs[i].count = 0;
157 		}
158 		/* initialize intc controller */
159 		intc_init();
160 		enable_interrupts();
161 	} else {
162 		puts("Undefined interrupt controller\n");
163 	}
164 	return 0;
165 }
166 
167 void interrupt_handler(void)
168 {
169 	int irqs = intc->ivr;	/* find active interrupt */
170 	int mask = 1;
171 	int value;
172 	struct irq_action *act = vecs + irqs;
173 
174 	debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
175 	      intc->iar, intc->mer);
176 #ifdef DEBUG
177 	R14(value);
178 #endif
179 	debug("Interrupt handler on %x line, r14 %x\n", irqs, value);
180 
181 	debug("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
182 	      (u32)act->handler, act->count, (u32)act->arg);
183 	act->handler(act->arg);
184 	act->count++;
185 
186 	intc->iar = mask << irqs;
187 
188 	debug("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
189 	      intc->ier, intc->iar, intc->mer);
190 #ifdef DEBUG
191 	R14(value);
192 #endif
193 	debug("Interrupt handler on %x line, r14 %x\n", irqs, value);
194 }
195 
196 #if defined(CONFIG_CMD_IRQ)
197 int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, const char *argv[])
198 {
199 	int i;
200 	struct irq_action *act = vecs;
201 
202 	if (irq_no) {
203 		puts("\nInterrupt-Information:\n\n"
204 		      "Nr  Routine   Arg       Count\n"
205 		      "-----------------------------\n");
206 
207 		for (i = 0; i < irq_no; i++) {
208 			if (act->handler != (interrupt_handler_t *)def_hdlr) {
209 				printf("%02d  %08x  %08x  %d\n", i,
210 				       (int)act->handler, (int)act->arg,
211 				       act->count);
212 			}
213 			act++;
214 		}
215 		puts("\n");
216 	} else {
217 		puts("Undefined interrupt controller\n");
218 	}
219 	return 0;
220 }
221 #endif
222