xref: /rk3399_rockchip-uboot/arch/microblaze/cpu/cache.c (revision a47a12becf66f02a56da91c161e2edb625e9f20c)
1 /*
2  * (C) Copyright 2007 Michal Simek
3  *
4  * Michal SIMEK <monstr@monstr.eu>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #include <common.h>
26 #include <asm/asm.h>
27 
28 int dcache_status (void)
29 {
30 	int i = 0;
31 	int mask = 0x80;
32 	__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
33 	/* i&=0x80 */
34 	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
35 	return i;
36 }
37 
38 int icache_status (void)
39 {
40 	int i = 0;
41 	int mask = 0x20;
42 	__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
43 	/* i&=0x20 */
44 	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
45 	return i;
46 }
47 
48 void	icache_enable (void) {
49 	MSRSET(0x20);
50 }
51 
52 void	icache_disable(void) {
53 	MSRCLR(0x20);
54 }
55 
56 void	dcache_enable (void) {
57 	MSRSET(0x80);
58 }
59 
60 void	dcache_disable(void) {
61 	MSRCLR(0x80);
62 }
63