1*e77e65dfSangelo@sysam.it /* 2*e77e65dfSangelo@sysam.it * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> 3*e77e65dfSangelo@sysam.it * 4*e77e65dfSangelo@sysam.it * SPDX-License-Identifier: GPL-2.0+ 5*e77e65dfSangelo@sysam.it * 6*e77e65dfSangelo@sysam.it */ 7*e77e65dfSangelo@sysam.it 8*e77e65dfSangelo@sysam.it #ifndef mcf5307_h 9*e77e65dfSangelo@sysam.it #define mcf5307_h 10*e77e65dfSangelo@sysam.it 11*e77e65dfSangelo@sysam.it /* 12*e77e65dfSangelo@sysam.it * Size of internal RAM (RAMBAR) 13*e77e65dfSangelo@sysam.it */ 14*e77e65dfSangelo@sysam.it #define INT_RAM_SIZE 4096 15*e77e65dfSangelo@sysam.it 16*e77e65dfSangelo@sysam.it /* Bit definitions and macros for SYPCR */ 17*e77e65dfSangelo@sysam.it #define SYPCR_SWTAVAL 0x02 18*e77e65dfSangelo@sysam.it #define SYPCR_SWTA 0x04 19*e77e65dfSangelo@sysam.it #define SYPCR_SWT(x) ((x&0x3)<<3) 20*e77e65dfSangelo@sysam.it #define SYPCR_SWP 0x20 21*e77e65dfSangelo@sysam.it #define SYPCR_SWRI 0x40 22*e77e65dfSangelo@sysam.it #define SYPCR_SWE 0x80 23*e77e65dfSangelo@sysam.it 24*e77e65dfSangelo@sysam.it /* Bit definitions and macros for CSMR */ 25*e77e65dfSangelo@sysam.it #define CSMR_V 0x01 26*e77e65dfSangelo@sysam.it #define CSMR_UD 0x02 27*e77e65dfSangelo@sysam.it #define CSMR_UC 0x04 28*e77e65dfSangelo@sysam.it #define CSMR_SD 0x08 29*e77e65dfSangelo@sysam.it #define CSMR_SC 0x10 30*e77e65dfSangelo@sysam.it #define CSMR_CI 0x20 31*e77e65dfSangelo@sysam.it #define CSMR_AM 0x40 32*e77e65dfSangelo@sysam.it #define CSMR_WP 0x100 33*e77e65dfSangelo@sysam.it 34*e77e65dfSangelo@sysam.it /* Bit definitions and macros for DACR (SDRAM) */ 35*e77e65dfSangelo@sysam.it #define DACR_PM_CONTINUOUS 0x04 36*e77e65dfSangelo@sysam.it #define DACR_IP_PRECHG_ALL 0x08 37*e77e65dfSangelo@sysam.it #define DACR_PORT_SZ_32 0 38*e77e65dfSangelo@sysam.it #define DACR_PORT_SZ_8 (1<<4) 39*e77e65dfSangelo@sysam.it #define DACR_PORT_SZ_16 (2<<4) 40*e77e65dfSangelo@sysam.it #define DACR_IMRS_INIT_CMD (1<<6) 41*e77e65dfSangelo@sysam.it #define DACR_CMD_PIN(x) ((x&7)<<8) 42*e77e65dfSangelo@sysam.it #define DACR_CASL(x) ((x&3)<<12) 43*e77e65dfSangelo@sysam.it #define DACR_RE (1<<15) 44*e77e65dfSangelo@sysam.it 45*e77e65dfSangelo@sysam.it /* Bit definitions and macros for CSCR */ 46*e77e65dfSangelo@sysam.it #define CSCR_BSTW 0x08 47*e77e65dfSangelo@sysam.it #define CSCR_BSTR 0x10 48*e77e65dfSangelo@sysam.it #define CSCR_BEM 0x20 49*e77e65dfSangelo@sysam.it #define CSCR_PS(x) ((x&0x3)<<6) 50*e77e65dfSangelo@sysam.it #define CSCR_AA 0x100 51*e77e65dfSangelo@sysam.it #define CSCR_WS ((x&0xf)<<10) 52*e77e65dfSangelo@sysam.it 53*e77e65dfSangelo@sysam.it /* Bit definitions for the ICR family of registers */ 54*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ 55*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ 56*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ 57*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ 58*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ 59*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ 60*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ 61*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ 62*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ 63*e77e65dfSangelo@sysam.it 64*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ 65*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ 66*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ 67*e77e65dfSangelo@sysam.it #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ 68*e77e65dfSangelo@sysam.it 69*e77e65dfSangelo@sysam.it #endif /* mcf5307_h */ 70*e77e65dfSangelo@sysam.it 71